Vertical Semiconductor Electrode Structure for Crack-Resistant Bonding

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Solution Overview

Problem

Existing semiconductor modules face issues with bonding reliability and thermal stress resistance, particularly in high-temperature operations, due to the use of gold layers that are costly and prone to cracking, leading to reduced heat dissipation and failure.

Innovation Solution

Incorporating a lowermost layer of copper and gold alloy in the lower electrode, along with a bonding layer composed of copper, tin, and nickel, which enhances bonding reliability and thermal stress resistance by suppressing crack formation and maintaining solder wettability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a gold layer is used in the lower electrode, then bonding reliability is improved, but cost increases and crack resistance deteriorates

Engineering Contradiction:
Improvebonding reliabilityVSAvoidcrack formation
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent applies composite materials by creating a multi-layer lower electrode structure consisting of a Cu-Ni alloy layer, a Cu-Sn alloy layer, and a Cu-Au alloy layer. Each layer serves specific functions: the Cu-Ni layer provides base adhesion, the Cu-Sn layer enhances bonding reliability and solder wettability, and the Cu-Au layer provides thermal stress resistance. This composite structure resolves the contradiction by combining materials with complementary properties rather than using a single gold layer.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent applies local quality by optimizing the composition and thickness of each layer in the multi-layer structure. The Cu-Sn alloy layer is specifically designed with controlled Sn content (1-20 at%) and thickness (0.1-5 μm) to provide localized bonding enhancement at the interface, while the Cu-Au alloy layer (0.1-5 μm thick) provides localized thermal stress resistance. This localized optimization allows each layer to address specific problems without requiring extensive gold throughout the entire structure.

Inventive Principle:
Principle #3Local quality

2Reliability

If a gold layer is used in the lower electrode, then bonding reliability is improved, but manufacturing cost increases

Engineering Contradiction:
Improvebonding reliabilityVSAvoidgold content
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent reduces gold content by replacing a substantial portion with copper-based alloy layers. The Cu-Ni alloy layer (Ni: 1-20 at%, thickness: 0.1-5 μm) and Cu-Sn alloy layer (Sn: 1-20 at%, thickness: 0.1-5 μm) provide bonding functionality that would otherwise require gold, thereby reducing the quantity and cost of gold while maintaining or improving bonding reliability.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent uses cheaper copper-based alloy materials (Cu-Ni, Cu-Sn) as替代 materials for expensive gold in the lower electrode structure. These copper-based layers provide the necessary bonding and thermal stress resistance functions at a lower cost, effectively replacing expensive materials with more economical alternatives that achieve the same or better performance.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Ease of manufacture

If existing bonding structures are used, then manufacturing is simplified, but thermal stress resistance deteriorates in high-temperature operations

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidthermal stress resistance
Core Design Contradiction:
Ease of manufactureVSTemperature

Solution Approach 1:

The patent applies composite materials by creating a multi-layer lower electrode structure consisting of a Cu-Ni alloy layer, a Cu-Sn alloy layer, and a Cu-Au alloy layer. Each layer serves specific functions: the Cu-Ni layer provides base adhesion, the Cu-Sn alloy layer enhances bonding reliability and solder wettability, and the Cu-Au alloy layer provides thermal stress resistance. This composite structure resolves the contradiction by combining materials with complementary properties rather than using a single gold layer.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent applies parameter changes by precisely controlling the composition and thickness parameters of each layer. The Cu-Sn alloy layer has Sn content controlled at 1-20 at% and thickness at 0.1-5 μm, while the Cu-Au alloy layer has Au content at 1-20 at% and thickness at 0.1-5 μm. These parameter optimizations enhance thermal stress resistance through controlled material properties while maintaining compatibility with existing manufacturing processes.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution improves the dTjP/C withstand value, ensuring enhanced bonding reliability and reduced solder erosion, thereby supporting high-temperature operations and miniaturization in semiconductor modules.

Implementation Method 1

a bonding layer composed of copper, tin, and nickel

Methodology Applied
Scientific EffectDiffusion: Diffusion

Implementation Method 2

a bonding layer composed of copper, tin, and nickel, which enhances bonding reliability

Methodology Applied
Scientific EffectAlloying:

Implementation Method 3

enhances bonding reliability and thermal stress resistance by suppressing crack formation

Methodology Applied
Scientific EffectThermal stress resistance:

Implementation Method 4

maintaining solder wettability

Methodology Applied
Scientific EffectSolder wettability: Wetting

Data Source

PatentUS20260082666A1Vertical device and semiconductor module
Publication Date: 2026.03.19 FUJI ELECTRIC CO LTD
  • US20260082666A1 patent drawing
  • US20260082666A1 patent drawing
  • US20260082666A1 patent drawing

AI summary

There is provided a vertical device including: a semiconductor substrate which has an upper surface and a lower surface; and a lower electrode which is provided on the entire lower surface of the semiconductor substrate, in which the lower electrode contains copper. The lower electrode may have a lowermost layer which is exposed at a surface that is farthest away from the lower surface of the semiconductor substrate, the lowermost layer may contain copper, a ratio of copper in the lowermost layer may be 50 wt% or more and 90 wt% or less, and a thickness of the lowermost layer may be 0.2 μm or more and 0.8 μm or less.