Vertically Stacked Faraday Shield for LDMOS Gate-Drain Capacitance
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Solution Overview
Problem
As semiconductor device dimensions shrink, existing Faraday shields for LDMOS devices struggle to provide effective shielding characteristics while maintaining cost-efficiency and timely manufacturing, leading to inadequate reduction of gate-to-drain capacitance and potential hot carrier injection.
Innovation Solution
A novel Faraday shield design featuring vertically oriented, stacked conductive features positioned between the gate electrode and drain region, aligned with source/drain conductors and contacts, which effectively reduces gate-to-drain capacitance and shields high electric fields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional Faraday shield designs are used, then manufacturing cost and time are controlled, but shielding effectiveness and gate-to-drain capacitance reduction are insufficient
Solution Approach 1:
The Faraday shield is segmented into multiple vertically stacked conductive features rather than using a single continuous structure. This segmentation allows the shield to achieve better shielding effectiveness through multiple shielding planes while maintaining manufacturing feasibility by forming each segment through separate processing steps
Solution Approach 2:
The invention transitions from traditional lateral Faraday shield extensions to a vertical stacking configuration. By orienting conductive features vertically and stacking them in the depth dimension, the shield achieves improved gate-to-drain capacitance reduction and shielding characteristics without significantly increasing lateral footprint or manufacturing complexity
2Volume of moving object
If device dimensions are shrunk, then integration density is improved, but shielding characteristics deteriorate
Solution Approach 1:
By moving the shielding function into the vertical dimension through stacked conductive features, the invention achieves effective shielding in a compact lateral footprint. The vertical stacking allows multiple shielding planes to be packed within the device depth, maintaining shielding effectiveness as device dimensions are shrunk
Solution Approach 2:
The vertically stacked conductive features are nested within the device structure, with each conductive segment positioned at different vertical levels. This nesting approach allows the Faraday shield functionality to be integrated within the existing device volume without requiring additional lateral space, enabling effective shielding in scaled-down devices
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The novel Faraday shield design reduces gate-to-drain capacitance by approximately 8% compared to traditional designs, enhancing RF performance and mitigating hot carrier injection, while maintaining manufacturing efficiency.
Implementation Method 1
A Faraday shield that is positioned laterally between the gate electrode and the drain region and above the isolation structure
Implementation Method 2
to screen the gate for drain potential and to move the high electric field away from the gate edge in an attempt to mitigate hot carrier injection at the drain edge under the gate
Data Source
AI summary
One illustrative device disclosed herein includes a transistor comprising a gate electrode and a drain region formed in a semiconducting substrate, an isolation structure formed in the substrate, wherein the isolation structure is laterally positioned between the gate electrode and the drain region, and a Faraday shield that is positioned laterally between the gate electrode and the drain region and above the isolation structure, wherein the Faraday shield has a long axis that is oriented substantially vertically relative to an upper surface of the substrate.