Dual-Gated Vertical Fe-FETs for Non-Volatile CAM Scaling

The patent transitions from planar 2D memory cell layouts to vertical 3D transistor structures. The vertical transistor extends in the vertical dimension with source and drain regions at different heights, allowing memory cells to be stacked vertically. This dimensional change increases storage density without further shrinking lateral process geometries, thereby reducing cost per bit while avoiding the associated scaling challenges.

The patent employs dual-gated vertical transistors where the threshold voltage can be dynamically adjusted by applying voltages to two independent gates. This parameter control allows optimization of device performance and memory cell operation without requiring further geometric scaling. The ability to tune threshold voltages independently enables precise control over read/write operations and match line sensing, resolving design challenges associated with scaled geometries.

The vertical transistor structure performs multiple functions within a single device: data storage in the channel region, threshold voltage control through dual gates, and integration with match line sensing circuitry. The source and drain regions serve both as charge storage elements and as connection points for bit line and complement bit line. This multi-functionality increases storage density while managing device complexity by consolidating functions rather than adding separate components.

The vertical transistor is segmented into distinct functional regions: source region, channel region, drain region, and two gate regions. Each segment performs a specific function - the source and drain store charge, the channel conducts current, and the gates control threshold voltage. This segmentation allows independent optimization of each region and simplifies the overall device design by dividing complex functionality into manageable, specialized components.