Vertical FET Split-Channel Antifuse for Leakage-Controlled Scaling
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Solution Overview
Problem
Conventional semiconductor devices face challenges in reducing transistor dimensions while maintaining performance, particularly in vertical field effect transistors (FETs), which limits their integration density and functionality in system-on-chip (SOC) applications.
Innovation Solution
The development of a vertical FET with a split-channel antifuse device, featuring a varying gate dielectric thickness, allows for controlled dielectric breakdown and reduced footprint, integrating an antifuse device with a vertical semiconductor channel and an electrically conductive gate, facilitating increased component density and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If vertical FET structure is used to reduce footprint, then device area is reduced, but integration density and functionality are limited
Solution Approach 1:
The patent combines a vertical FET structure with an integrated antifuse device, merging two separate functions (transistor operation and memory storage) into a single unified structure. This allows the device to serve dual purposes, thereby increasing integration density without requiring additional device area.
Solution Approach 2:
The vertical FET structure is designed to perform multiple functions: it operates as a transistor for logic operations and simultaneously integrates an antifuse device for memory storage. This multi-functionality enables higher productivity and integration density within the reduced footprint.
2Productivity
If conventional antifuse integration is used, then component density increases, but current leakage occurs
Solution Approach 1:
The gate dielectric is designed with non-uniform thickness, having a first thickness in the channel region and a second (greater) thickness in the antifuse region. This local variation in dielectric quality allows the structure to prevent current leakage in the antifuse region while maintaining proper transistor operation in the channel region.
Solution Approach 2:
The patent changes the physical parameter of gate dielectric thickness to different values in different regions. By increasing the dielectric thickness in the antifuse region, the breakdown voltage is increased, thereby preventing unwanted current leakage while still allowing controlled breakdown for programming when needed.
3Ease of manufacture
If uniform gate dielectric thickness is used, then manufacturing is simplified, but dielectric breakdown control is reduced
Solution Approach 1:
The gate dielectric is engineered with spatially varying thickness, having different thickness values in different regions. This local differentiation provides precise control over dielectric breakdown characteristics in the antifuse region while maintaining manufacturability through established semiconductor fabrication techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the integration density and functionality of SOC applications by controlling dielectric breakdown and reducing current leakage, achieving a reduced footprint and improved performance in vertical FETs.
Implementation Method 1
The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate
Data Source
AI summary
A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.