Vertical FET Dual-Gate Feedback Sub-kTq Switching
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Solution Overview
Problem
Conventional FETs have a thermally limited subthreshold slope of about 60-70 mV per decade, limiting their ability to achieve arbitrarily fast transitions between 'OFF' and 'ON' states, resulting in a trade-off between low power and high performance.
Innovation Solution
A vertical field effect transistor (VFET) with a dual-gate feedback loop mechanism is fabricated, utilizing a recursive feedback loop between potential barriers and charge carriers to achieve a sub-kT/q sub-threshold slope, enabling faster transitions and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional FET structure is used, then manufacturing process is simple, but subthreshold slope is thermally limited to 60-70 mV per decade
Solution Approach 1:
The gate is divided into two separate gates (first gate and second gate) positioned at different locations along the channel. This segmentation allows independent control of potential barriers at different positions, enabling precise control of the subthreshold slope through coordinated gating actions while maintaining a manufacturable structure using standard semiconductor fabrication processes.
Solution Approach 2:
The invention transitions from a conventional planar gate structure to a vertical field effect transistor architecture where gates are positioned at different vertical and horizontal locations along the channel. This dimensional change enables the feedback loop mechanism to achieve sub-kT/q subthreshold slope by creating and controlling potential barriers in three-dimensional space, overcoming the thermal limitation of conventional two-dimensional gate structures.
2Device complexity
If conventional single-gate structure is used, then device complexity is low, but transition speed between ON and OFF states is limited
Solution Approach 1:
The dual-gate structure implements a feedback loop mechanism where the first gate creates a potential barrier that controls carrier injection into the channel, and the second gate modulates the channel potential in response to carrier accumulation. This feedback mechanism enables abrupt transitions between ON and OFF states by creating a regenerative effect that amplifies small voltage changes, achieving fast switching speeds while maintaining manageable device complexity through systematic design.
3Use of energy by moving object
If conventional FET is used, then power consumption can be kept low, but performance and switching speed are compromised
Solution Approach 1:
The invention changes the electrical parameters of the transistor by introducing a feedback mechanism that dynamically adjusts potential barriers through dual-gate control. This allows the device to achieve high switching performance with low power consumption by operating in a regime where small voltage changes produce large current modulations, effectively decoupling the traditional trade-off between power and performance through parameter optimization enabled by the feedback loop architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual-gate feedback loop mechanism allows for abrupt increases in diode current, enhancing the transistor's ability to rapidly switch between states, thereby improving performance while maintaining low power consumption.
Implementation Method 1
utilizing a recursive feedback loop between potential barriers and charge carriers to achieve a sub-kT/q sub-threshold slope
Implementation Method 2
A vertical field effect transistor (VFET) with a dual-gate feedback loop mechanism is fabricated
Data Source
AI summary
Fabricating a feedback field effect transistor includes receiving a semiconductor structure including a substrate, a first source/drain disposed on the substrate, a fin disposed on the first source/drain, and a hard mask disposed on a top surface of the fin. A bottom spacer is formed on a portion of the first source/drain. A first gate is formed upon the bottom spacer. A sacrificial spacer is formed upon the first gate, a gate spacer is formed on the first gate from the sacrificial spacer, and a second gate is formed on the gate spacer. The gate spacer is disposed between the first gate and the second gate. A top spacer is formed around portions of the second gate and hard mask, a recess is formed in the top spacer and hard mask, and a second source/drain is formed in the recess.