Vertical FET Gate Electrode Isolation via Dielectric Spacer
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Solution Overview
Problem
In vertical-transport field-effect transistors, maintaining electrical isolation between the gate electrode and the contact becomes increasingly difficult as the distance between them is scaled down, leading to potential electrical shorts due to lithography overlay shifts and compromised isolation.
Innovation Solution
A method involving the formation of a semiconductor fin with a gate stack that includes a laterally recessed gate electrode and a dielectric spacer to create a cavity, ensuring electrical isolation between the gate electrode and the contact landing area, allowing for closer proximity without risking shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between the gate electrode and the contact is scaled down, then the device size is reduced and productivity is improved, but the reliability of electrical isolation deteriorates due to lithography overlay shifts
Solution Approach 1:
A dielectric spacer is introduced as an intermediary element between the gate electrode and the contact. This spacer physically separates the two conductive elements, maintaining electrical isolation even when their lateral distance is minimized. The spacer acts as a mediator that prevents direct electrical contact while allowing the structures to be positioned close together for scaling purposes.
Solution Approach 2:
Instead of relying solely on lateral separation in the horizontal plane to maintain isolation, the solution transitions to vertical separation by adding a dielectric spacer in the vertical dimension. This dimensional transition allows the gate electrode and contact to be laterally adjacent while maintaining electrical isolation through the vertically positioned spacer layer.
2Reliability
If the gate electrode section is laterally recessed to form a cavity, then the dielectric spacer can be formed to maintain isolation, but the device structure becomes more complex
Solution Approach 1:
The gate electrode section is laterally recessed in advance to pre-form a cavity that will later receive the dielectric spacer. This preliminary action creates the necessary space for the isolation element before final contact formation, ensuring that the spacer can be properly positioned and integrated into the device structure without requiring complex post-processing steps.
Data Source
AI summary
Structures for a vertical-transport field-effect transistor and methods for forming a structure for a vertical-transport field-effect transistor. A semiconductor fin is formed on a source/drain region. A gate stack is deposited that coats the semiconductor fin and a contact landing area of the source/drain region adjacent to the semiconductor fin. The gate stack is patterned to remove the gate stack from the contact landing area and to form a gate electrode having a section adjacent to the contact landing area. The section of the gate electrode is laterally recessed to form a cavity, and a dielectric spacer is formed in the cavity.