Vertical FET Structure With Shortened Gate Overlap
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Solution Overview
Problem
The complexity of manufacturing semiconductor devices at a miniaturized scale leads to increased yield loss, reduced reliability of electrical interconnections, and low testing coverage, necessitating improvements in device structure and manufacturing methods to enhance robustness, reduce costs, and shorten processing time.
Innovation Solution
A semiconductor device design featuring a vertical stack of upper and lower FETs with a common gate and independently controlled source/drain regions, utilizing separate metal power rails to decrease resistance and power consumption, and a shortened gate to reduce stray capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate length is extended to improve control over source/drain regions, then the control capability is improved, but the stray capacitance increases
Solution Approach 1:
The gate is segmented into multiple sections (first gate section, second gate section, third gate section) with different lengths extending beyond the active region. This segmentation allows each section to serve different functions: the first section provides control while the second and third sections are shortened to reduce overlapping area and stray capacitance with source/drain contacts, thus resolving the contradiction between control capability and stray capacitance reduction.
2Productivity
If the device is miniaturized to increase functional density, then the functional density is improved, but the manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar device layout to vertical stacking, where multiple FETs are stacked in the vertical dimension rather than arranged horizontally. This dimensional change increases functional density without proportionally increasing manufacturing complexity, as the stacked structure can be formed through sequential deposition and patterning processes that build upon each other vertically.
Solution Approach 2:
Multiple FET structures are nested vertically within each other, with upper FETs positioned above lower FETs in a stacked configuration. This nesting approach allows multiple functional units to occupy a smaller footprint area while using standardized fabrication processes, thereby increasing functional density without linearly increasing manufacturing complexity.
3Reliability
If the gate overlaps more with source/drain contacts to improve electrical connection, then the electrical connection is improved, but the stray capacitance increases
Solution Approach 1:
Different sections of the gate have different local qualities in terms of extension length. The first gate section extends by a first length, the second gate section extends by a second length, and the third gate section extends by a third length, where these lengths are different. This local differentiation allows optimal electrical connection in some regions while minimizing stray capacitance in other regions, resolving the contradiction between electrical connection quality and stray capacitance reduction.
Data Source
AI summary
A semiconductor structure includes a first transistor and a second transistor over the first transistor. The first transistor includes: a gate extending in a first direction; a first active region arranged extending in a second direction; and a first conductive line and a second conductive line arranged on two sides of the first active region. The second transistor includes: the gate; a second active region; and a third conductive line and a fourth conductive line arranged on two sides of the second active region. The gate has a first portion and a second portion extending beyond the first active region by a first length and a second length greater than the first length. One of the first to fourth conductive lines has a third portion and a fourth portion extending beyond the first active region by a third length and a length greater than the third length.