Vertical FET Layout for Lower Stray Capacitance in Semiconductor Cells
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Solution Overview
Problem
The increasing complexity and miniaturization of semiconductor devices lead to challenges such as high yield loss, reduced reliability of electrical interconnections, and low testing coverage, necessitating improvements in device robustness, manufacturing cost, and processing time.
Innovation Solution
A semiconductor device design featuring a vertical stack of upper and lower FETs with a common gate and independently controlled source/drain regions, along with separate top and bottom power rails and a shortened gate to reduce resistance and stray capacitance, enhancing power efficiency and speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the gate length is reduced to improve speed, then the switching speed increases, but the stray capacitance between gate and source/drain contacts increases
Solution Approach 1:
The patent transitions from a planar gate configuration to a three-dimensional folded gate structure. The gate is folded back underneath the source/drain contacts, changing the spatial dimension of the gate configuration. This dimensional change allows the gate to achieve longer effective length (improving speed) while reducing the overlapping area with source/drain contacts (reducing stray capacitance), as the folded portions are positioned underneath rather than alongside the contacts.
Solution Approach 2:
The gate is segmented into multiple portions (first gate portion, second gate portion, third gate portion) that are folded and positioned at different locations. This segmentation allows each gate portion to contribute to the effective gate length while minimizing overlap with source/drain contacts. The segmented folded structure achieves both high speed (through long effective gate length) and low stray capacitance (through reduced overlapping area).
2Productivity
If the device is miniaturized to increase functional density, then the number of devices per chip area increases, but the manufacturing complexity and yield loss increase
Solution Approach 1:
The patent merges multiple FETs into a vertical stack configuration where multiple transistors share common structures (substrate, source/drain regions, gate). This merging reduces the total device area (increasing functional density) while the standardized vertical fabrication process maintains manufacturing simplicity. The shared structures reduce the number of separate fabrication steps required compared to discrete planar devices.
Solution Approach 2:
The patent transitions from planar lateral arrangement of devices to vertical stacking in the third dimension. This dimensional change increases functional density by utilizing vertical space rather than horizontal chip area. The vertical stack configuration maintains manufacturing simplicity through standardized vertical fabrication processes, avoiding the increased complexity that would result from attempting to pack more planar devices into smaller areas.
3Reliability
If the gate overlaps more with source/drain contacts to improve electrical connection, then the connection reliability improves, but the stray capacitance increases
Solution Approach 1:
The patent introduces an intermediary structure (the folded gate configuration) that mediates between the need for good electrical connection and the need to minimize stray capacitance. The gate is folded underneath the source/drain contacts, creating an intermediary positioning that provides electrical connection through the vertical structure while minimizing lateral overlap. This intermediary configuration achieves both reliable electrical connection and reduced stray capacitance simultaneously.
Data Source
AI summary
A layout method includes: generating a design data including an electronic circuit; and generating a design layout by placing a cell corresponding to the electronic circuit. The cell includes a first transistor and a second transistor over the first transistor. The first transistor includes a gate extending in a first direction, a first active region arranged in a first layer and extending in a second direction, and a first conductive line and a second conductive line arranged on two sides of the first active region. The second transistor includes the gate, a second active region arranged in a second layer over the first layer and extending in the second direction, and a third conductive line and a fourth conductive line arranged on two sides of the second active region. At least one of the four conductive lines includes a first portion non-overlapped with the gate in the first direction.