III-V Vertical FET Tunable Bandgap Source Drain
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Solution Overview
Problem
Traditional CMOS techniques for planar FET devices face limitations in scaling transistor density due to constraints on gate pitch, spacer thickness, and source/drain size, while vertical FET devices offer potential for increased density but require advanced materials to enhance electron mobility and reduce leakage currents.
Innovation Solution
The development of vertical FET devices with tunable bandgap source/drain regions using III-V compound semiconductor materials, where the upper source/drain region is engineered with additional elements to increase its bandgap relative to the lower region, allowing for epitaxial growth to control the bandgap of the upper source/drain region for improved performance and reduced leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical FET devices are used to increase transistor density, then scaling is improved, but drain leakage increases due to lower bandgap materials
Solution Approach 1:
The patent applies local quality by creating distinct bandgap regions within the source/drain structure. The upper source/drain region uses a first III-V material with a lower bandgap for high electron mobility and conductivity, while the lower source/drain region uses a second III-V material with a higher bandgap to minimize leakage. This spatial differentiation of material properties allows each region to optimize for its specific function, resolving the contradiction between maintaining high transistor density and reducing drain leakage.
Solution Approach 2:
The patent employs composite materials by combining two different III-V compound semiconductor materials with different bandgap energies in a vertical heterostructure. The composite source/drain structure consists of InGaAs (lower bandgap) for the upper region and InAlAs or InP (higher bandgap) for the lower region. This composite approach enables simultaneous achievement of high electron mobility in the upper region and low leakage in the lower region, directly addressing the technical contradiction.
2Speed
If III-V compound semiconductor materials are used to increase electron mobility, then performance is improved, but bandgap control becomes challenging
Solution Approach 1:
The patent applies parameter changes by systematically varying the compositional parameters of III-V semiconductor materials to achieve desired bandgap values. Specifically, the upper source/drain region uses InGaAs with optimized In/Ga ratio for maximum electron mobility, while the lower source/drain region uses InAlAs or InP with adjusted Al content or structure to achieve higher bandgap. This precise control of material composition parameters enables simultaneous optimization of electron mobility and bandgap control.
Solution Approach 2:
The patent segments the source/drain region into two distinct vertical zones with different material compositions and bandgap characteristics. The upper segment (higher in the structure) uses material optimized for electron transport, while the lower segment (closer to the channel) uses material optimized for leakage suppression. This segmentation allows independent optimization of each region's material parameters, making bandgap control more manageable while maintaining high electron mobility where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables increased transistor density and reduced power consumption by minimizing drain leakage through bandgap tuning, balancing performance and power efficiency in vertical FET devices.
Implementation Method 1
The additional element increases a bandgap of the second type of III-V compound semiconductor material that forms the upper source/drain region relative to a bandgap of the first type of III-V compound semiconductor material that forms the lower source/drain region and the vertical semiconductor fin
Implementation Method 2
epitaxially growing a lower source/drain region on a semiconductor substrate, epitaxially growing a vertical semiconductor fin on an upper surface of the lower source/drain region, and epitaxially growing an upper source/drain region on an upper region of the vertical semiconductor fin
Data Source
AI summary
Vertical field effect transistor (FET) device with tunable bandgap source/drain regions are provided, as well as methods for fabricating such vertical FET devices. For example, a vertical FET device includes a lower source/drain region formed on a substrate, a vertical semiconductor fin formed on the lower source/drain region, and an upper source/drain region formed on an upper region of the vertical semiconductor fin. The lower source/drain region and vertical semiconductor fin are formed of a first type of III-V semiconductor material. The upper source/drain region is formed of a second type of III-V semiconductor material which comprises the first type of III-V semiconductor material and at least one additional element that increases a bandgap of the second type of III-V semiconductor material of the upper source/drain region relative to a bandgap of the first type of III-V compound semiconductor material of the lower source/drain region and the vertical semiconductor fin.