Vertical Fin CMOS ESD Protection Diode Design
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Solution Overview
Problem
Conventional ESD protection diodes are ineffective at low operating voltages, particularly in advanced vertical FIN technologies, as they require higher voltages to trigger and provide inadequate protection for CMOS devices operating below 2.5 V, leading to potential damage due to electrostatic discharge.
Innovation Solution
The use of vertically stacked PN junctions bounded by semiconductor fins for ohmic contacts, formed through epitaxial growth with highly doped N and P regions, and Schottky diodes with guard rings in the FIN body for accurate junction formation and rapid response to electrostatic discharge events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection diodes are used, then they can provide electrostatic discharge protection, but they require higher trigger voltages that are ineffective for low operating voltage CMOS devices
Solution Approach 1:
The patent changes the trigger voltage parameter of the ESD protection diode by using vertical FIN CMOS technology with highly doped N and P regions. This creates a low breakdown voltage structure that triggers at voltages compatible with advanced CMOS operating levels (below 2.5V), making the protection effective for low-voltage devices while preventing damage from electrostatic discharge
2Reliability
If vertical FIN CMOS technology is used for ESD protection, then accurate junction formation and rapid response are achieved, but device complexity increases
Solution Approach 1:
The patent transitions from conventional planar ESD diode structures to a vertical FIN CMOS architecture. By moving the junction formation into the vertical dimension with fins extending upward from the substrate, the design achieves more precise junction length control and faster response times while the systematic fin-based approach manages the inherent structural complexity
3Ease of manufacture
If PN junctions are formed through ion implantation, then manufacturing is simplified, but junction length definition accuracy is reduced
Solution Approach 1:
The patent introduces an intermediary approach where vertical FIN structures serve as physical templates or masks during the ion implantation process. The fin geometry itself defines the junction length boundaries, combining the manufacturing simplicity of ion implantation with the precision of structurally-defined junction dimensions, achieving both ease of manufacture and manufacturing precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures reliable ESD protection by accurately defining the PN junction length and response threshold, preventing damage to CMOS devices by effectively managing electrostatic discharge at lower operating voltages, thus enhancing the integrity and operation of coupled electronics.
Implementation Method 1
formed through epitaxial growth with highly doped N and P regions
Implementation Method 2
Electrostatic discharge is the sudden flow of electricity between electrically charged objects which can cause damage to the IC or other sensitive electronic devices
Data Source
AI summary
Embodiments include a method and resulting structures for vertical fin CMOS technology for electrostatic discharge protection. In a non-limiting embodiment, forming a first set of semiconductor fins vertically extending from a substrate, and forming a second set of semiconductor fins vertically extending from the substrate, the distance between the first set of fins and the second set of fins defines a length of a junction. Embodiments also include forming a first epitaxy layer on the substrate, and forming a second epitaxy layer atop a portion of the first epitaxy layer, wherein a PN junction is formed between the first epitaxy layer and the second epitaxy layer, wherein a length of the PN junction is defined by the first set of semiconductor fins and the second semiconductor fins. Embodiments include forming a first metal contact atop the first epitaxy layer, and forming a second metal contact atop the second epitaxy layer.