Vertical FinFET Strained Channel Epitaxial Growth
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current integrated circuit technologies face challenges in enhancing carrier mobility and device performance in vertical field effect transistors, particularly due to limitations in strain induction in transistor channels as feature sizes shrink.
Innovation Solution
The method involves forming a strained channel in vertical FinFETs by epitaxially growing silicon germanium on a silicon substrate for p-type FETs and silicon on a silicon germanium substrate for n-type FETs, utilizing lattice mismatch to create compressive or tensile strain, followed by the formation of gate stacks and spacers to finalize the transistor structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes are reduced to continue scaling, then device density increases, but carrier mobility deteriorates due to limited strain induction capability
Solution Approach 1:
The patent transitions from planar strain induction to three-dimensional vertical strain induction by growing SiGe channel layers on vertically oriented dummy fins. This dimensional change enables effective strain induction in scaled devices where planar approaches fail, maintaining carrier mobility while achieving higher device density through continued scaling.
Solution Approach 2:
The patent changes the material composition parameter by introducing SiGe alloys with varying germanium concentrations in the channel layers. This parameter change enables controlled strain induction in the vertical direction, improving carrier mobility in scaled devices where traditional silicon channels no longer provide sufficient performance.
2Reliability
If SiGe channel layers are grown on silicon dummy fins, then compressive strain is induced improving hole mobility, but the process complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming dummy fins with specific geometries and materials before channel growth, and by pre-configuring the epitaxial growth conditions for SiGe layers. These preliminary actions enable subsequent strain induction and gate formation to proceed more efficiently, reducing overall process complexity despite the advanced materials involved.
Solution Approach 2:
The patent uses dummy fins as intermediary structures that facilitate the transition from standard silicon processing to strained SiGe channel formation. These dummy fins serve as temporary substrates that enable controlled SiGe growth and strain induction, while being removable afterward, thus managing process complexity through a mediating structure.
3Reliability
If multiple gate stacks are formed to achieve vertical FinFET structure, then device performance improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the gate formation process into multiple discrete gate stack formation steps, each targeting specific regions of the device. This segmentation allows for controlled deposition and patterning of gate materials on different portions of the channel, enabling vertical FinFET structure formation while managing alignment precision through staged processing rather than requiring single-step perfect alignment.
Solution Approach 2:
The patent replaces mechanical alignment methods with epitaxial growth-based self-alignment for forming the strained channel layers on dummy fins. The epitaxial process inherently aligns the channel material with the underlying dummy fin structure, reducing the precision requirements for subsequent gate stack formation and minimizing alignment complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves carrier mobility and device performance by inducing strain in the channel, leading to enhanced performance of vertical FinFETs, allowing for better hole mobility in p-type and electron mobility in n-type transistors.
Implementation Method 1
A channel is epitaxially grown on the dummy fin structure in such a manner as to create a strain on the channel
Implementation Method 2
utilizing lattice mismatch to create compressive or tensile strain
Implementation Method 3
inducing strain in the channel of a transistor is useful to improve carrier mobility and device performance
Data Source
AI summary
A transistor in an integrated circuit device is formed using fabrication processes that include techniques to create a strain in the channel material, thereby improving the performance of the transistor. In one or more embodiments, an initial transistor structure is formed including a substrate, a dummy fin, and a hard mask. The dummy fin structure is narrowed. A channel is epitaxially grown on the dummy fin structure to create a strain on the channel. A first gate stack is formed over the channel. The hard mask and dummy fin are removed. A second gate stack is formed over the channel. Excess material is removed from the second gate stack. The formation of the transistor is finalized using a variety of techniques.