Vertical GAA Memory Cell for Stable PUF Fingerprints

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Solution Overview

Problem

SRAM cells used as PUF devices exhibit low stability due to variations in electrical properties influenced by environmental conditions, posing challenges in maintaining a consistent unique digital fingerprint.

Innovation Solution

A vertical gate-all-around (GAA) memory cell with a resistor and a GAA transistor is used, leveraging manufacturing variation-induced randomness in resistance for stable PUF values, unaffected by environmental conditions, and allowing high memory density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If SRAM cells are used as PUF devices, then manufacturing variation can generate unique digital fingerprints, but stability of PUF values deteriorates due to environmental condition variations

Engineering Contradiction:

Improvestability of PUF valuesVSAvoidenvironmental condition variations

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent transitions from using SRAM cell threshold voltage variations to using GAA transistor channel length variations as the source of PUF randomness. This parameter change from electrical property variations to dimensional variations fundamentally improves stability because dimensional parameters are less sensitive to environmental conditions like temperature and voltage fluctuations.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent replaces the electrical mechanism (SRAM threshold voltage) with a geometric/mechanical mechanism (GAA transistor channel length). The physical dimension of the channel, determined during fabrication, becomes the source of uniqueness rather than electrical properties that fluctuate with environmental conditions.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Quantity of substance

If vertical GAA memory cell structure is adopted, then memory density is improved, but device complexity increases

Engineering Contradiction:

Improvememory densityVSAvoidvertical gate-all-around structure

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent employs vertical stacking of memory cells in the third dimension rather than planar arrangement. By growing nanoscale channels vertically and wrapping gates around them, the design achieves higher density without proportionally increasing lateral footprint, effectively trading vertical fabrication complexity for horizontal space efficiency.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250338469A1Vertical gate-all-around (GAA) memory cell and method for forming the same

Publication Date: 2025.10.30 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Various embodiments of the present disclosure are directed to a vertical gate-all-around (GAA) memory cell. A middle conductor overlies a lower conductor and decreases in width towards the lower conductor to culminate in a point spaced from the lower conductor. An insulator structure is between the lower conductor and the middle conductor. A semiconductor channel overlies the middle conductor, and a gate electrode laterally surrounds the semiconductor channel on a sidewall of the semiconductor channel. A gate dielectric layer separates the gate electrode from the semiconductor channel, and an upper conductor overlies the semiconductor channel. The lower and middle conductors and the insulator structure correspond to a resistor, whereas the middle conductor, the upper conductor, the gate electrode, the gate dielectric layer, and the semiconductor channel correspond to a transistor atop the resistor.