Vertical-Gate Charge Transfer for Miniaturized Image Sensors
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Solution Overview
Problem
In miniaturized imaging elements, the charge transfer section struggles to efficiently transfer charges from the photoelectric conversion section to the charge holding section, impairing light detection characteristics.
Innovation Solution
The semiconductor device incorporates a charge transfer section with a MOS transistor comprising a first and second semiconductor region and multiple vertical gates embedded in the semiconductor substrate, configured to transfer charges efficiently by aligning the vertical gates in parallel and ensuring uniform characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel size is reduced to meet higher image definition demands, then image definition is improved, but charge transfer performance deteriorates
Solution Approach 1:
The patent transitions from planar gate electrodes to vertically extending gate electrodes that penetrate through the semiconductor substrate. This dimensional change allows the gate to control charge transfer in the depth direction, enabling effective charge transfer in miniaturized pixels where horizontal space is limited.
Solution Approach 2:
The charge transfer section is divided into multiple regions with different potential depths. The patent configures photoelectric conversion sections with deeper potentials and charge holding sections with shallower potentials, creating a potential gradient that facilitates efficient charge transfer while maintaining compact pixel dimensions.
2Quantity of substance
If photoelectric conversion section potential is deepened to improve charge holding capacity in miniaturized pixels, then charge holding capacity is improved, but charge transfer difficulty increases
Solution Approach 1:
The vertical gate structure extends in the depth direction to provide sufficient gate control over charges in deep potential wells. This allows the photoelectric conversion section to maintain deep potential for high charge capacity while the vertical gate ensures effective transfer control without increasing planar device complexity.
Solution Approach 2:
The patent changes the gate electrode orientation from horizontal to vertical, fundamentally altering the control mechanism. This parameter change enables the gate to exert control over charges in the depth direction, solving the transfer difficulty caused by deepened potential wells.
3Productivity
If multiple vertical gates are disposed in parallel to improve charge transfer performance, then charge transfer efficiency is improved, but device complexity increases
Solution Approach 1:
Multiple vertical gate electrodes are merged into a single integrated gate structure that controls the charge transfer section. This unified structure simplifies the device by reducing the number of independently controlled gates while maintaining the parallel charge transfer capability through the vertical configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances charge transfer performance, maintaining light detection characteristics even in reduced pixel sizes by optimizing the charge transfer process.
Implementation Method 1
a gate electrode disposed embedded in the vicinity of the front surface of the semiconductor substrate with a bottom portion formed in the vicinity of the first semiconductor region
Data Source
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AI summary
The present disclosure improves light detection characteristics of a semiconductor device. A semiconductor device includes a charge transfer section. The charge transfer section includes a MOS transistor including a first semiconductor region disposed in a semiconductor substrate, a second semiconductor region disposed in the vicinity of a front surface of the semiconductor substrate, and a plurality of vertical gates, each being a gate electrode disposed embedded in the vicinity of the front surface of the semiconductor substrate with a bottom portion formed in the vicinity of the first semiconductor region, the charge transfer section being configured to transfer a charge from one of the first semiconductor region and the second semiconductor region to the other. The plurality of vertical gates are disposed in parallel.