Vertical Transistor Gate Contact Structures for Easier Lithography
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Solution Overview
Problem
Traditional planar structures for semiconductor devices face limitations in memory density and scaling, leading to challenges in forming effective gate contacts for vertically oriented transistors.
Innovation Solution
The development of novel gate contact formation structures and methods for vertical transistors, including extended gate regions, merged gates, and self-aligned contact films, to facilitate easier and more efficient gate contact formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional planar structures are used for semiconductor devices, then manufacturing processes are simpler, but memory density and scaling are limited
Solution Approach 1:
The patent transitions from traditional planar (2D) transistor structures to vertically oriented (3D) transistor structures. The gate contact structure extends vertically along the sidewalls of semiconductor pillars, enabling three-dimensional integration that dramatically increases device density while maintaining compatibility with existing manufacturing processes
Solution Approach 2:
The gate contact structure is formed by nesting multiple layers within each other: the first gate contact portion is positioned within a dielectric layer, which is then covered by a planarized dielectric layer, and the second gate contact portion extends through this planarized layer. This nested arrangement allows complex 3D structures to be built using sequential deposition and planarization steps
2Quantity of substance
If vertically oriented devices are used to increase memory density, then device integration density improves, but gate contact formation becomes challenging due to topography
Solution Approach 1:
The patent performs preliminary planarization by depositing a planarized dielectric layer over the vertically oriented gate structure before forming subsequent contacts. This preliminary action creates a flat surface that simplifies the formation of additional contacts and interconnect structures, eliminating the need to work directly with the complex vertical topography
Solution Approach 2:
The planarized dielectric layer serves as an intermediary between the vertical gate structure and the horizontal contact structures. This intermediate layer mediates the transition from vertical to horizontal orientations, allowing contacts to be formed on a planar surface while still accessing the vertical gate structure through controlled etching
3Manufacturing precision
If self-aligned anisotropic etch is used to pattern gates on sidewalls, then gate alignment precision improves, but spacer-like gate pieces leave limited contact area
Solution Approach 1:
The patent extends the gate contact structure from the traditional horizontal plane into the vertical dimension. The gate contact portions follow the vertical sidewalls of the semiconductor pillars and extend upward, creating a three-dimensional contact structure that provides sufficient contact area while maintaining the precise alignment achieved by self-aligned etching
Solution Approach 2:
The patent performs preliminary planarization with a planarized dielectric layer before forming subsequent contacts. This creates a flat reference surface that allows for the formation of additional contacts and interconnect structures without being constrained by the underlying vertical topography, enabling sufficient contact area to be achieved
Data Source
AI summary
Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.