Vertical Transistor Gate Contact Structures for Complex Pillar Topography
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Solution Overview
Problem
Traditional planar semiconductor device structures face limitations in achieving high memory densities, leading to the adoption of vertically oriented transistors, which pose challenges in gate contact formation due to the complex topography of tall semiconductor pillars.
Innovation Solution
The development of novel gate contact formation structures and methods for vertical transistors, including extended gate regions, planarized dielectric layers, and merged gates between pillars, allowing for efficient gate contact formation without additional masking steps and alleviating photolithography challenges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically oriented transistors are used to increase memory density, then the number of devices per chip increases, but gate contact formation becomes difficult due to complex topography
Solution Approach 1:
The patent transitions from traditional planar gate contacts to vertical gate contacts that extend along the sidewalls of semiconductor pillars. The gate structure is extended into the vertical dimension, creating a three-dimensional configuration where the gate contact wraps around or contacts the pillar sidewalls, thereby adapting to the vertical transistor architecture and enabling reliable electrical connection despite the complex topography.
Solution Approach 2:
The patent employs preliminary actions by forming sacrificial spacers and masking structures before final gate contact formation. These preliminary structures guide the etching and deposition processes to create precise gate contact patterns on the pillar sidewalls, ensuring accurate alignment and reliable contact formation before the actual gate electrode is deposited.
2Manufacturing precision
If self-aligned anisotropic etch with over-etch is used to pattern gates, then gate alignment is improved, but spacer-like gate film pieces remain on pillar sidewalls creating complexity
Solution Approach 1:
The patent selectively removes the spacer-like gate film pieces that remain on the pillar sidewalls after self-aligned anisotropic etching. Through controlled etching processes and selective removal techniques, these excess spacer fragments are extracted or removed, leaving only the desired gate structures while eliminating the complexity they introduce to subsequent manufacturing steps.
Solution Approach 2:
The patent applies controlled over-etching followed by selective removal. The initial self-aligned anisotropic etch uses sufficient over-etch to ensure complete pattern transfer and alignment, creating the spacer-like pieces. Then, a subsequent selective etching step removes these excess pieces partially, keeping only the necessary gate structures. This two-stage approach balances the benefits of over-etching for alignment with the need to eliminate excess material.
Data Source
AI summary
Structures and methods that facilitate the formation of gate contacts for vertical transistors constructed with semiconductor pillars and spacer-like gates are disclosed. In a first embodiment, a gate contact rests on an extended gate region, a piece of a gate film, patterned at a side of a vertical transistor at the bottom of the gate. In a second embodiment, an extended gate region is patterned on top of one or more vertical transistors, resulting in a modified transistor structure. In a third embodiment, a gate contact rests on a top surface of a gate merged between two closely spaced vertical transistors. Optional methods and the resultant intermediate structures are included in the first two embodiments in order to overcome the related topography and ease the photolithography. The third embodiment includes alternatives for isolating the gate contact from the semiconductor pillars or for isolating the affected semiconductor pillars from the substrate.