Vertical Gate E-Fuse Array Circuit for Compact Data Storage
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Solution Overview
Problem
Existing e-fuse array circuits face challenges in programming and reading data due to dimensional restrictions, as they require large transistors or amplifiers to detect resistance changes, which occupy excessive space and complicate the design.
Innovation Solution
The e-fuse array circuit incorporates e-fuse transistors of a vertical gate type and selection transistors of a buried gate type, with a metal line for efficient voltage supply and reduced space occupation, allowing for effective data storage and switching operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If large transistors are used to recognize data based on resistance changes, then data recognition capability is improved, but circuit area increases
Solution Approach 1:
The patent transitions from planar transistor configuration to vertical channel transistor configuration, moving the current path from two-dimensional to three-dimensional space. This vertical channel structure allows the transistor to achieve sufficient current modulation capability for data recognition while occupying minimal planar area, effectively resolving the contradiction between measurement precision and circuit area.
Solution Approach 2:
The patent changes the channel length parameter from conventional lateral dimensions to vertical dimensions, enabling the transistor to achieve the required current modulation capability with a compact footprint. This parameter transformation allows small-sized transistors to provide sufficient signal strength for direct sensing without requiring area-increasing measures.
2Measurement precision
If amplifiers are added to sense current flowing through transistors, then data sensing capability is improved, but device complexity increases
Solution Approach 1:
The patent extracts and removes the amplifier component from the e-fuse structure, achieving direct current sensing without signal amplification. By designing the transistor with enhanced current modulation capability through vertical channel configuration, the system can directly detect the current state without requiring additional amplification stages, thereby eliminating device complexity while maintaining sensing capability.
Solution Approach 2:
The transistor itself is designed to provide sufficient current modulation capability to enable direct sensing, making the system self-sufficient without external amplifiers. The vertical channel transistor generates adequate current signal strength inherently, allowing the sensing circuit to directly read the resistance state without additional active components.
3Ease of manufacture
If high voltage is applied to program e-fuse, then programming capability is improved, but risk of gate oxide destruction increases
Solution Approach 1:
The patent applies high voltage only locally to the gate terminal during programming operations, while the drain-source terminals operate at low voltages. This localized high voltage application enables effective gate oxide modification for programming while preventing excessive voltage stress on other transistor regions, thereby maintaining gate oxide integrity and reliability during the programming process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables efficient data storage and switching with reduced space requirements, allowing for the efficient supply of high voltages and optimal switching characteristics, addressing the dimensional restrictions of previous designs.
Implementation Method 1
An e-fuse stores a data by using a transistor and changing the resistance between a gate and a drain/source
Implementation Method 2
a selection transistor of a buried gate type configured to have a gate for receiving a voltage of a word line gate line and electrically connect/disconnect the other one between the drain terminal and the source terminal with a bit line
Data Source
AI summary
An e-fuse array circuit includes: an e-fuse transistor of a vertical gate type configured to have a gate for receiving a voltage of a program gate line and have one between a drain terminal and a source terminal floating; and a selection transistor of a buried gate type configured to have a gate for receiving a voltage of a word line gate line and electrically connect/disconnect the other one between the drain terminal and the source terminal with a bit line.