Vertical Gate Image Sensor Layout for Higher Quantum Efficiency
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Solution Overview
Problem
Current image sensor fabrication methods face challenges in achieving high quantum efficiency and cost-effectiveness due to complex processes and the need for multiple masks, which increase production costs and reduce process windows.
Innovation Solution
The method involves forming a vertical gate structure on a semiconductor substrate with a light-sensitive element, using a few masks to create a post structure and a floating node, and employing high-k dielectric materials for the gate dielectric layer, allowing the light-sensitive element to occupy a larger area and improving signal transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional image sensor fabrication methods are used with multiple masks, then manufacturing precision can be maintained, but device complexity and production costs increase
Solution Approach 1:
The patent combines multiple mask alignment steps into a single maskless alignment process. The alignment mark is formed directly on the substrate during the same process that creates the light-sensitive element structure, eliminating the need for separate mask alignment steps. This merging of operations reduces both the number of process steps and the complexity of equipment required.
Solution Approach 2:
The patent extracts the alignment function from the mask-based process and integrates it directly into the deposition process. By forming the alignment mark and the light-sensitive element structure in the same process step, the patent removes the intermediate mask alignment operations, thereby simplifying the overall fabrication process.
2Reliability
If the light-sensitive element area is increased to improve quantum efficiency, then sensing performance improves, but peripheral circuit integration becomes more difficult
Solution Approach 1:
The patent transitions from a planar layout to a three-dimensional vertical structure. The light-sensitive element is formed as a vertical columnar structure extending through multiple layers, with the alignment mark positioned at the top surface. This vertical arrangement allows the light-sensitive element to occupy a larger effective area for light sensing while maintaining a compact footprint that accommodates peripheral circuits in the horizontal plane.
Solution Approach 2:
The patent segments the image sensor into distinct functional regions: a central region containing the vertically extended light-sensitive element for high quantum efficiency, and surrounding regions containing peripheral circuits. This segmentation allows each region to be optimized independently - the light-sensitive element maximizes light capture area while peripheral circuits are arranged in the available space around it.
3Productivity
If a single process step is used to form both alignment mark and light-sensitive element, then productivity increases, but manufacturing precision requirements become more stringent
Solution Approach 1:
The alignment mark structure serves dual purposes: it acts as both the alignment reference and part of the light-sensitive element structure. The same deposition process that creates the light-sensitive element column also forms the alignment mark on top of it. This self-service approach eliminates the need for separate alignment mark formation processes, thereby improving productivity without sacrificing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces fabrication costs by using fewer masks and enhances quantum efficiency by enabling the light-sensitive element to occupy a larger area, improving signal transfer and overall image sensor performance.
Implementation Method 1
employing high-k dielectric materials for the gate dielectric layer
Data Source
AI summary
A device includes a substrate, a light sensitive element, a pinning region, a lightly-doped region, a floating node, and a gate stack. The light sensitive element is in the substrate. The pinning region is in the substrate and is over the light sensitive element. The lightly-doped region is laterally adjacent the pinning region. The floating node is in the pinning region, the floating node being spaced from and surrounded by the lightly-doped region. A first portion of the pinning region is between the floating node and the lightly-doped region. The gate stack is over the first portion of the pinning region.