Vertical-Gate MOSFET Structure for Low-Cost Channel Control
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Solution Overview
Problem
The high manufacturing cost of finFETs due to increased processing steps limits the adoption in cost-sensitive applications like CMOS image sensors, where low noise and high reliability are crucial.
Innovation Solution
A vertical-gate transistor with a gate electrode structure comprising a horizontal portion and first and second vertical portions is introduced, which surrounds at least three surfaces of the channel region, reducing noise and increasing control without significantly increasing manufacturing costs by requiring only one additional masking structure and removal step compared to planar MOSFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If finFETs are used instead of planar MOSFETs, then device control and noise reduction are improved, but manufacturing cost increases
Solution Approach 1:
The gate electrode structure transitions from a planar two-dimensional configuration to a three-dimensional vertical configuration with horizontal and vertical portions. This dimensional change enables the gate to control the channel from multiple directions (top and sidewalls), improving device control and noise reduction while maintaining compatibility with existing manufacturing processes through modified deposition and etching steps
2Object-affected harmful factors
If finFETs are used instead of planar MOSFETs, then noise is reduced, but manufacturing complexity increases
Solution Approach 1:
The gate electrode is segmented into distinct horizontal and vertical portions that can be formed through separate deposition and patterning steps. This segmentation allows for optimized formation of each portion independently while maintaining overall structural integrity, reducing manufacturing complexity compared to forming a complete fin structure
3Reliability
If vertical-gate transistor design is implemented, then device reliability is enhanced, but processing steps increase
Solution Approach 1:
The horizontal and vertical portions of the gate electrode are merged into a single continuous conductive structure formed through integrated deposition and patterning processes. This merging reduces the number of discrete manufacturing steps compared to forming separate fin structures while maintaining the three-dimensional vertical gate configuration that enhances device reliability
Data Source
AI summary
In some embodiments, the present disclosure relates to a device having a semiconductor substrate including a frontside and a backside. On the frontside of the semiconductor substrate are a first source/drain region and a second source/drain region. A gate electrode is arranged on the frontside of the semiconductor substrate and includes a horizontal portion, a first vertical portion, and a second vertical portion. The horizontal portion is arranged over the frontside of the semiconductor substrate and between the first and second source/drain regions. The first vertical portion extends from the frontside towards the backside of the semiconductor substrate and contacts the horizontal portion of the gate electrode structure. The second vertical portion extends from the frontside towards the backside of the semiconductor substrate, contacts the horizontal portion of the gate electrode structure, and is separated from the first vertical portion by a channel region of the substrate.