Vertical Gate Stacking in Semiconductor Memory Devices
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Solution Overview
Problem
The challenge is to enhance the integration of semiconductor memory devices while maintaining performance and reducing costs, particularly in the structure of transistors that control memory cell operations.
Innovation Solution
The semiconductor memory device incorporates a cell structure with multiple gate electrodes stacked vertically and a channel structure penetrating these electrodes, along with a peripheral circuit structure featuring an active area, gate structure, source/drain area, insulating spacer, conductive spacer, and contact, all electrically connected to improve integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional planar transistor structures are used, then manufacturing is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional vertically stacked gate electrode structures. Multiple gate electrodes are stacked in the vertical direction above the channel structure, enabling increased integration density by utilizing the third dimension (vertical stacking) rather than only horizontal expansion. This dimensional change allows more memory cells to be packed into the same footprint area.
2Productivity
If vertically stacked gate electrodes are implemented, then integration density increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary patterning actions to define the positions of gate electrodes, channel structures, and source/drain regions before vertical stacking. Mask patterns and etch processes are pre-configured to ensure precise alignment of multiple gate electrodes in the vertical direction. The insulating spacers are formed in advance to provide physical references and spacing control, enabling accurate positioning of subsequent layers without requiring ultra-precise alignment during assembly.
Solution Approach 2:
The patent introduces insulating spacers as intermediary structures between gate electrodes and source/drain regions. These spacers serve as mediators that provide both electrical isolation and physical positioning references. The spacers are formed conformally on the sidewalls of gate structures, automatically establishing precise spacing and alignment relationships without requiring direct measurement or adjustment, thus reducing manufacturing precision requirements.
3Reliability
If insulating spacers and conductive spacers are added, then electrical isolation and connection are improved, but device structure complexity increases
Solution Approach 1:
The patent designs the insulating spacers to serve multiple functions simultaneously: they provide electrical isolation between adjacent gate electrodes and source/drain regions, act as physical spacers to define spacing, and serve as alignment references for subsequent patterning steps. The conductive spacers similarly provide both electrical connection pathways and structural support. This multi-functionality reduces the need for separate dedicated structures, thereby limiting the increase in overall device complexity.
Solution Approach 2:
The patent merges the formation of insulating spacers and conductive spacers into an integrated spacer structure system. Both types of spacers are formed using similar conformal deposition and etching processes, and they work together as a unified spacing and isolation system. The insulating and conductive portions are positioned adjacently and function complementarily, reducing the need for separate processing sequences and simplifying the overall manufacturing flow despite the increased structural detail.
Data Source
AI summary
Provided a semiconductor memory device. The semiconductor memory device comprises a cell structure, and a peripheral circuit structure electrically connected to the cell structure. The cell structure includes a plurality of gate electrodes stacked in a vertical direction and spaced apart from each other in the vertical direction, a channel structure penetrating the plurality of gate electrodes in the vertical direction, and a bit-line connected to the channel structure. The peripheral circuit structure includes an active area, a gate structure on the active area, the gate structure intersecting the active area, a source/drain area on at least one side of the gate structure and in the active area, an insulating spacer covering the gate structure, a conductive spacer on a sidewall of the insulating spacer and electrically connected to the source/drain area, and a contact electrically connected to the conductive spacer. At least a portion of a topmost surface of the insulating spacer is coplanar with at least a portion of a topmost surface of the conductive spacer.