Vertical Gate-Around Transistor for High-Density 3D Memory
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Solution Overview
Problem
Conventional 3D semiconductor memory devices face challenges in achieving a large on/off ratio while maintaining a reduced transistor layout size, which is essential for high-density integration and scalability beyond the 20 nm technology node.
Innovation Solution
A 3D semiconductor memory device with a vertical-type gate-around transistor and vertical annular variable resistance unit configuration, where adjacent transistors share a common source region and gates are isolated by an insulating layer, allowing for a smaller layout size and controlled on/off current ratio through adjustments in channel width and length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional 3D memory structures are used, then high-density integration is achieved, but the on/off ratio decreases and layout size increases
Solution Approach 1:
The patent transitions from planar 2D transistor structures to vertical 3D gate-around transistor structures. The gate electrode wraps around the channel in a cylindrical configuration, utilizing the vertical dimension to increase the effective gate control area without increasing the planar footprint. This dimensional transition enables both small layout size and high on/off ratio by providing superior gate control over the channel.
Solution Approach 2:
The gate-around transistor structure nests the gate electrode around the channel region, with the gate wrapping partially or fully around the channel in a cylindrical configuration. This nested arrangement maximizes the gate-channel interface area within a compact footprint, enabling high on/off ratio control while maintaining small layout size for high-density integration.
2Ease of operation
If PN junction diodes are used for cell selection, then cell selection is achieved, but memory cell height and thickness increase
Solution Approach 1:
The patent extracts and eliminates the PN junction diode component from the memory cell structure. Instead of using a diode for cell selection, the design relies on the gate-around transistor's inherent selectivity through voltage control. This removal of the diode component reduces the memory cell height and eliminates the need for additional layers, enabling better multi-level stacking.
Solution Approach 2:
The gate-around transistor serves multiple functions: it provides cell selection through voltage-controlled switching, enables high-density integration through compact footprint, and maintains reliability through superior gate control. This multi-functional design eliminates the need for separate diode components, reducing overall cell height and simplifying the structure.
3Ease of manufacture
If high temperature ion implantation is used for PN junction formation, then junction formation is achieved, but previously-formed memory cell performance is affected
Solution Approach 1:
The gate-around transistor structure and variable resistance material layers are formed first, establishing the memory cell functionality. Subsequent processing steps are designed to occur at lower temperatures that do not degrade previously-formed structures. This preliminary formation of sensitive components protects them from high-temperature damage in later manufacturing steps.
Solution Approach 2:
The patent changes the temperature parameter of subsequent processing steps from high temperature (required for PN junction formation) to lower temperatures compatible with previously-formed memory cells. This parameter modification enables continued manufacturing of additional memory cell levels without degrading existing structures, improving overall device reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a high-density integration of memory cells with improved reliability and reduced layout size, facilitating multi-state operations while maintaining a large on/off current ratio, thus addressing the limitations of conventional 3D memory technologies.
Implementation Method 1
A resistance random access memory (RRAM) distinguishes two states by a reversible conversion of the storage medium between a high resistance and a low resistance under the effect of an electric signal.
Data Source
AI summary
The present application discloses a 3D semiconductor memory device having 1T1R memory configuration based on a vertical-type gate-around transistor, and a manufacturing method thereof. A on/off current ratio can be well controlled by changing a width and a length of a channel of the gate-around transistor, so as to facilitate multi-state operation of the 1T1R memory cell. Moreover, the vertical transistor has a smaller layout size than a horizontal transistor, so as to reduce the layout size effectively. Thus, the 3D semiconductor memory device can be integrated into an array with a high density.