Vertical Half-Bridge Semiconductor Package for Smaller PCB Footprint
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Solution Overview
Problem
Semiconductor packages with increased functionality require a smaller footprint on higher-level circuit boards, as the trend towards higher integration and power consumption in processing units leads to space constraints and design challenges due to the area occupied by highside, lowside, and driver devices.
Innovation Solution
A semiconductor package with a vertical mounting arrangement featuring a low voltage contact pad, high voltage contact pad, output contact pad, and control contact pads, where the first and second transistor devices are stacked perpendicularly to the lower surface, allowing for a reduced footprint by enabling vertical placement on the board, along with a power stage including a half-bridge circuit and control devices for efficient power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If transistor devices are arranged horizontally on the substrate, then the package provides sufficient electrical connections and functionality, but the package occupies a large area on the circuit board
Solution Approach 1:
The patent transitions from a conventional horizontal planar arrangement of transistor devices on the substrate to a vertical three-dimensional arrangement where transistor devices are stacked perpendicular to the substrate surface. This dimensional change allows multiple transistor devices to be positioned in the vertical direction while maintaining their electrical connections, thereby significantly reducing the package footprint on the circuit board without compromising functionality
2Area of stationary object
If the package footprint is reduced for higher integration, then more packages can be mounted on the circuit board, but the electrical connections and current management become more challenging
Solution Approach 1:
By stacking transistor devices vertically perpendicular to the substrate, the patent reduces lateral space requirements while maintaining robust electrical connections through vertical interconnect structures. The contact pads and conductive paths are arranged to provide reliable electrical connectivity between the stacked transistor devices and the substrate, ensuring current management reliability despite the compact footprint
Solution Approach 2:
The patent implements a nested arrangement where transistor devices are stacked one above another in a vertical configuration, with each device positioned within the vertical envelope of the package. This nesting approach allows multiple functional devices to occupy a compact vertical space while maintaining their individual electrical connection paths to the substrate through shared or distributed contact pads
3Area of stationary object
If transistor devices are stacked vertically, then the package occupies smaller board area, but the manufacturing and assembly process becomes more complex
Solution Approach 1:
The vertical stacking architecture enables a modular manufacturing approach where transistor devices can be fabricated separately and then assembled in the vertical direction. This dimensional reconfiguration allows for standardized vertical interconnect structures and contact pad arrangements that can be manufactured using established semiconductor fabrication techniques, making the complex vertical arrangement manufacturable through systematic process design
Data Source
Figure 1A~1B
Figure 1C~1E
Figure 1F~1G
AI summary
In an embodiment, a semiconductor package comprises a lower surface comprising a low voltage contact pad, a high voltage contact pad, an output contact pad and at least one control contact pad. The semiconductor package further comprises a halfbridge circuit comprising a first transistor device having a first major surface and a second transistor device having a first major surface, the first and second transistor devices being electrically coupled in series at an output node and a control device that is electrically coupled to the first transistor device and the second transistor device. The first major surface of the first transistor device and of the second transistor device are arranged substantially perpendicularly to the lower surface of the semiconductor package.