Vertical HHMT Structure for Higher Breakdown and Lower Dark Current
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Solution Overview
Problem
Existing high hole mobility transistors (HHMTs) based on Group III nitride semiconductors face limitations due to defects in their structures, which restrict their application ranges, particularly in high energy, high voltage, or high frequency applications.
Innovation Solution
A high hole mobility transistor design featuring a vertical interface with a channel layer and a channel supply layer forming a vertical two-dimensional hole gas (2DHG), where electrodes are positioned to maximize voltage withstand and reduce dark current, incorporating a nucleation layer, buffer layer, and insulating layers to enhance device integrity and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If conventional planar device structures are used, then manufacturing is simpler, but voltage withstand capacity and performance in high energy applications are limited
Solution Approach 1:
The patent transitions from conventional planar (2D) device structures to a vertical (3D) structure where the channel extends in the vertical direction. This dimensional change enables higher voltage withstand capacity by increasing the breakdown voltage through the vertical channel length, while also improving device performance in high energy and high frequency applications without proportionally increasing manufacturing complexity.
2Reliability
If Group III nitride semiconductor materials are used, then high breakdown electric field and high mobility are achieved, but structural defects limit application ranges
Solution Approach 1:
The patent modifies key structural parameters including the channel layer thickness (50-200 nm), channel supply layer composition (AlGaN with varying Al content), and interface orientation ((000-1) plane). These parameter changes optimize the balance between achieving high breakdown electric field intensity and reducing structural defects, thereby expanding the application range to include high energy, high voltage, and high frequency applications.
3Speed
If two-dimensional hole gas is formed at the interface, then high mobility and high response speed are achieved, but dark current increases
Solution Approach 1:
The patent introduces a channel supply layer (AlGaN) as an intermediary between the channel layer and the contact structures. This intermediary layer helps manage the two-dimensional hole gas formation at the interface, maintaining high mobility and response speed while reducing dark current through optimized carrier confinement and reduced leakage paths.
4Reliability
If vertical interface structure is implemented, then substrate influence is minimized and performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by creating a specific vertical interface structure with the channel layer having a thickness of 50-200 nm and the channel supply layer with controlled Al content gradients. This localized structural optimization at the critical interface region minimizes substrate influence and improves device performance while concentrating manufacturing precision requirements to specific critical dimensions that can be controlled through selective epitaxial growth processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design significantly improves voltage withstand capacity and reduces dark current, allowing for better performance in high energy and high frequency applications while minimizing the influence of the substrate, thus overcoming traditional planar device limitations.
Implementation Method 1
Polar semiconductors have many unique properties. Particularly importantly, fixed polarized charges are present at a surface of the polar semiconductor or at an interface of two different polar semiconductors. These fixed polarized charges may attract movable electrons or hole carriers, thus forming a two-dimensional electron gas 2DEG or a two-dimensional hole gas 2DHG.
Implementation Method 2
By using a vertical interface structure, the influence of the substrate can be minimized, thereby overcoming the limitations of traditional planar devices.
Data Source
AI summary
The present disclosure relates to a semiconductor device and a method of fabricating the same. The semiconductor device includes: a substrate including a vertical interface; a channel layer disposed outside the vertical interface; and a channel supply layer disposed outside the channel layer; wherein a vertical two-dimensional electron gas 2DEG or two-dimensional hole gas 2DHG is formed in the channel layer adjacent to an interface between the channel layer and the channel supply layer.