Vertically Oriented Inductor Fabrication for Chip Area Reduction
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Solution Overview
Problem
Conventional semiconductor IC components, such as transformers and inductors, face issues like excess space consumption, poor device performance, inadequate shielding, and high fabrication costs due to inefficiencies in chip area utilization and increased losses from eddy currents.
Innovation Solution
The development of vertically-oriented transformers and inductors with variable metal width coils and interconnect structures that reduce eddy current losses and improve coupling factors, allowing for more efficient chip area use and higher impedance transformation ratios, along with the implementation of shielding structures to minimize noise and interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional planar inductors and transformers are used, then fabrication is simpler, but chip area consumption is excessive
Solution Approach 1:
The patent transitions from conventional planar (2D) inductor and transformer designs to three-dimensional vertically-oriented structures. The inductors are formed with vertical vias and horizontal conductive layers stacked in multiple levels, while transformers utilize vertically-oriented magnetic cores with windings in different vertical planes. This dimensional change dramatically reduces chip area consumption by utilizing the vertical dimension for component placement and interconnections.
2Loss of energy
If conventional inductor structures are used, then fabrication is easier, but eddy current losses are high
Solution Approach 1:
The inductor structure is segmented into multiple conductive layers separated by dielectric materials, with vertical vias connecting horizontal conductive segments. This segmentation breaks up continuous current paths that would generate eddy currents, forcing current to flow through controlled vertical interconnections. The segmented structure reduces eddy current losses by disrupting the formation of large circulating current loops while maintaining the required inductance through the stacked geometry.
3Reliability
If conventional transformers are used, then coupling factor is insufficient, but vertically-oriented structures increase fabrication difficulty
Solution Approach 1:
The transformer structure employs nested windings where multiple conductive layers are stacked vertically around a central magnetic core, with each layer nested within the vertical space occupied by adjacent layers. This nested configuration maximizes the coupling between primary and secondary windings by placing them in close proximity in the vertical dimension, achieving high coupling factors while utilizing standard semiconductor fabrication processes for forming the stacked structure.
4Object-affected harmful factors
If shielding structures are added, then noise and interference are reduced, but fabrication complexity increases
Solution Approach 1:
The shielding structures are merged with the existing interconnect layers and device structures rather than being added as separate components. Conductive shielding layers are integrated into the dielectric stacks between active layers, and ground connections are combined with existing via structures. This merging approach provides effective electromagnetic shielding and noise reduction while utilizing the same fabrication processes already required for the active devices, avoiding additional fabrication complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
These solutions result in reduced chip area consumption, lower substrate losses, improved high-frequency performance, and enhanced impedance transformation capabilities, while also reducing thermal noise and allowing for more precise resonant frequency adjustment.
Implementation Method 1
an inductor coil that is wound substantially in a vertical plane that is orthogonal to the horizontal surface of the substrate
Implementation Method 2
a capacitor disposed proximate to the inductor coil, the capacitor having an anode component and a cathode component
Data Source
AI summary
The present disclosure involves a method of fabricating a semiconductor device. The method includes providing a substrate having a horizontal surface. The method includes forming an interconnect structure over the horizontal surface of the substrate. The forming the interconnect structure includes forming an inductor coil that is wound substantially in a vertical plane that is orthogonal to the horizontal surface of the substrate. The forming the interconnect structure includes forming a capacitor disposed proximate to the inductor coil. The capacitor has an anode component and a cathode component. The inductor coil and the capacitor each include a plurality of horizontally extending elongate members.