Vertical Inductor in Semiconductor Interconnect Layer
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Solution Overview
Problem
Integrated inductors in semiconductor devices often suffer from low Q factor due to eddy current losses and occupy significant die area, limiting design flexibility and performance.
Innovation Solution
A method of forming a high Q factor inductor within a semiconductor device by creating a conductive layer in a wound configuration with vertical separation from the semiconductor die, using an encapsulant and insulating layers to reduce eddy current losses and increase inductive performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If an inductor is integrated within the semiconductor die, then the device can be miniaturized and integrated, but the Q factor decreases due to eddy current losses
Solution Approach 1:
The patent moves the inductor from the two-dimensional plane of the semiconductor die to a three-dimensional structure above the die surface. The inductor is formed in an interconnect layer that is vertically separated from the die by an encapsulant, transitioning from planar integration to vertical stacking. This dimensional change eliminates eddy current losses in the die while maintaining compact form factor.
2Productivity
If an inductor is integrated within the semiconductor die, then integration density increases, but the die area consumed increases
Solution Approach 1:
The inductor is relocated from the die plane to a vertical interconnect layer above the die. This uses the third dimension (height) for inductor placement, freeing up die area while maintaining electrical integration. The encapsulant enables this vertical separation while providing structural support.
Solution Approach 2:
The encapsulant acts as an intermediary element that enables the inductor to be positioned above the die. It provides the necessary vertical separation, structural support, and electrical isolation between the die and the inductor in the interconnect layer, allowing compact three-dimensional integration.
3Area of stationary object
If the inductor is placed close to the semiconductor die, then the device footprint is reduced, but eddy current losses increase
Solution Approach 1:
The inductor is positioned in a vertical interconnect layer separated from the die by the encapsulant thickness. This vertical separation maintains a compact horizontal footprint while eliminating the harmful close-proximity eddy current effects by moving the inductor to a different vertical plane above the die surface.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach enhances the Q factor of inductors, reduces eddy current losses, and increases design flexibility by allowing for a more compact and efficient integration of inductive components within semiconductor devices.
Implementation Method 1
integrated die inductors often suffer with low Q factor, due in part to eddy current losses
Data Source
AI summary
A semiconductor device has an adhesive layer formed over a carrier. A semiconductor die has bumps formed over an active surface of the semiconductor die. The semiconductor die is mounted to the carrier with the bumps partially disposed in the adhesive layer to form a gap between the semiconductor die and adhesive layer. An encapsulant is deposited over the semiconductor die and within the gap between the semiconductor die and adhesive layer. The carrier and adhesive layer are removed to expose the bumps from the encapsulant. An insulating layer is formed over the encapsulant. A conductive layer is formed over the insulating layer in a wound configuration to exhibit inductive properties and electrically connected to the bumps. The conductive layer is partially disposed within a footprint of the semiconductor die. The conductive layer has a separation from the semiconductor die as determined by the gap and insulating layer.