Vertically Oriented Integrated Capacitors for High Density
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Solution Overview
Problem
There is a need for large value integrated passive devices that do not consume significant silicon area, as existing solutions like planar metal-insulator-metal capacitors occupy substantial space and require costly integration methods.
Innovation Solution
The development of a semiconductor device with vertically oriented capacitors, comprising the formation of vertical conductive structures, an insulating layer, and a conductive layer, which extends beyond the footprint of the interconnect structures, allowing for higher capacitance density without increasing die size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If planar metal-insulator-metal capacitors are used to achieve large value capacitance, then the capacitance value is improved, but the silicon area occupied increases significantly
Solution Approach 1:
The patent transitions from planar (2D) capacitor structures to three-dimensional vertically oriented capacitor structures. By stacking conductive layers and insulating materials vertically, the capacitor extends into the third dimension (height), enabling large capacitance values without proportionally increasing the silicon footprint. The conductive layer extends beyond the footprint of the vertical interconnect structures, creating a vertically oriented capacitor that utilizes vertical space rather than lateral space.
2Quantity of substance
If planar metal-insulator-metal capacitors are used for large value applications, then the capacitance value is improved, but the integration cost increases due to required surface mount technology
Solution Approach 1:
The patent merges the capacitor structure with the semiconductor device fabrication process itself. The vertically oriented capacitor is formed using the same front-end manufacturing steps that create the semiconductor circuits, including depositing conductive and insulating layers. This integration eliminates the need for separate surface mount technology processes, reducing manufacturing complexity and cost while achieving large capacitance values directly within the semiconductor device.
Data Source
AI summary
A semiconductor device includes conductive pillars disposed vertically over a seed layer, a conformal insulating layer formed over the conductive pillars, and a conformal conductive layer formed over the conformal insulating layer. A first conductive pillar, the conformal insulating layer, and the conformal conductive layer constitute a vertically oriented integrated capacitor. The semiconductor device further includes a semiconductor die or component mounted over the seed layer, an encapsulant deposited over the semiconductor die or component and around the conformal conductive layer, and a first interconnect structure formed over a first side of the encapsulant. The first interconnect structure is electrically connected to a second conductive pillar, and includes an integrated passive device. The semiconductor device further includes a second interconnect structure formed over a second side of the encapsulant opposite the first side of the encapsulant.