Vertical Interconnect Semiconductor Packaging for Compact Reliability
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Solution Overview
Problem
Conventional semiconductor packages face issues of high cost, decreased reliability, and large package sizes, leading to suboptimal performance.
Innovation Solution
The proposed solution involves a semiconductor device structure comprising a first substrate with a conductive structure, a second substrate with a conductive structure, a vertical interconnect coupling both substrates, and an encapsulant covering the interconnect, with exposed ports for communication, along with a method of manufacturing that includes attaching electronic components and forming encapsulants to secure and protect the interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor packages are used, then manufacturing cost is reduced, but reliability decreases and package size increases
Solution Approach 1:
The patent transitions from conventional lateral interconnect arrangements to vertical interconnect structures, utilizing the third dimension (vertical axis) to reduce the lateral footprint of the package. This dimensional change allows for higher density interconnections without increasing package area, thereby improving reliability while maintaining compact size.
Solution Approach 2:
The patent implements a stacked architecture where multiple substrates and electronic components are vertically nested within a compact enclosure. The first substrate, second substrate, and various components are arranged in layers, with the encapsulant nesting all elements within a small volume, achieving high integration density without increasing package footprint.
2Reliability
If conventional semiconductor packages are used, then manufacturing cost is reduced, but performance decreases
Solution Approach 1:
The patent employs preliminary formation of conductive structures and interconnects on substrates before final assembly. The conductive structures are pre-formed on the first and second substrates, and the encapsulant is prepared in advance, enabling more efficient assembly processes that reduce manufacturing complexity and cost despite the advanced package architecture.
Solution Approach 2:
The encapsulant serves multiple functions simultaneously: it provides mechanical support, environmental protection, electrical insulation, and structural integration for the vertical interconnect structure. This multi-functionality reduces the need for additional separate components, simplifying manufacturing and reducing overall cost.
3Volume of stationary object
If package size is reduced, then device integration is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the semiconductor device into distinct functional segments: first substrate with conductive structure, second substrate with conductive structure, vertical interconnect layer, and encapsulant. This segmentation allows each component to be optimized and manufactured separately using standard processes, reducing overall manufacturing complexity despite the compact integrated structure.
Solution Approach 2:
The patent merges multiple functions into the encapsulant material, which simultaneously provides structural support, environmental sealing, electrical insulation, and mechanical protection for the vertical interconnect. This consolidation reduces the number of separate manufacturing steps and components, simplifying production while achieving compact packaging.
Data Source
AI summary
In one example, an electronic device, comprises a first substrate comprising a first conductive structure, a second substrate comprising a second conductive structure, wherein the first substrate is over the second substrate, a first electronic component between the first substrate and the second substrate, a vertical interconnect between the first substrate and the second substrate, wherein the vertical interconnect is coupled with the first conductive structure and the second conductive structure, and an encapsulant between the first substrate and the second substrate and covering the vertical interconnect. A vertical port on the first electronic component is exposed by an aperture of the first substrate. Other examples and related methods are also disclosed herein.