Vertical Local Interconnect Layout for Lower Gate-Drain Capacitance
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Solution Overview
Problem
Parasitic impedance in semiconductor materials of field-effect transistors (FETs) negatively affects the performance of integrated circuits, specifically reducing oscillation frequency.
Innovation Solution
The integrated circuit design incorporates a vertical local interconnection that connects front-side and back-side source/drain epitaxies, reducing the overlapping area with gate components to minimize parasitic capacitance and enhance oscillation frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a conventional planar interconnection structure is used, then the manufacturing process is simple, but the parasitic capacitance between gate and drain is high
Solution Approach 1:
The patent transitions from a conventional planar (2D) interconnection structure to a vertical (3D) interconnection structure. The interconnection extends vertically through the substrate, connecting front-side and back-side circuits, thereby reducing the horizontal overlapping area between gate and drain regions and minimizing parasitic capacitance.
Solution Approach 2:
The interconnection structure is segmented into multiple portions: a first portion extending from the front surface, a second portion within the substrate, and a third portion extending to the back surface. This segmentation allows the interconnection to navigate through the substrate efficiently while minimizing overlap with active circuit regions.
2Object-affected harmful factors
If the overlapping area between interconnection and gate component is reduced, then parasitic capacitance decreases, but the interconnection path becomes more complex
Solution Approach 1:
By moving the interconnection path to the vertical dimension rather than keeping it planar, the patent successfully reduces gate-to-drain capacitance without significantly increasing manufacturing complexity. The vertical routing through the substrate provides a direct path that avoids lateral overlap with gate regions.
3Speed
If the oscillation frequency is increased, then the response speed improves, but parasitic impedance negatively affects this improvement
Solution Approach 1:
The patent employs a thin-film vertical interconnection structure that minimizes the cross-sectional area of the conductive path. This reduces the parasitic inductance and resistance, allowing higher oscillation frequencies and faster response speeds without being limited by parasitic impedance.
Data Source
AI summary
An integrated circuit includes a plurality of transistors and a vertical local interconnection. The transistors include a plurality of gate components, a plurality of front-side source/drain epitaxies and a plurality of back-side source/drain epitaxies, wherein the front-side source/drain epitaxies are closer to a front-side of the integrated circuit than the back-side source/drain epitaxies. The vertical local interconnection connects a first connected-one of the front-side source/drain epitaxies with a second connected-one of the back-side source/drain epitaxies. A covered-one of the gate components is located between the first connected-one and the second connected-one, the covered-one comprises an front-side portion, a back-side portion and a covered portion connecting the front-side portion with the back-side portion, and the vertical local interconnection crosses the covered portion and exposes the front-side portion and the back-side portion.