Vertical Interconnect Packaging with Rounded Cavity
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Solution Overview
Problem
Conventional semiconductor package structures face challenges in miniaturization, reliability, and cost-effectiveness, particularly in portable devices, where they struggle to achieve high packaging density, low profile, and improved performance while maintaining competitive pressures.
Innovation Solution
The method involves providing a substrate with an integrated circuit, attaching a vertical interconnect, forming an encapsulation that covers the interconnect, and creating a rounded cavity with a curved side within the encapsulation, allowing the interconnect to be exposed, which enhances connectivity and reliability through a locking function.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional semiconductor package structures are used, then packaging density can be increased, but miniaturization and low profile are compromised
Solution Approach 1:
The patent transitions from conventional planar packaging to a three-dimensional vertical architecture by stacking multiple integrated circuit dies vertically and connecting them through vertical interconnects. This dimensional change enables higher packaging density without proportionally increasing the horizontal footprint, thereby achieving miniaturization while maintaining high component density.
Solution Approach 2:
The patent implements package-on-package (POP) architecture where multiple semiconductor packages are stacked and nested vertically, with each package containing integrated circuit dies and interconnect structures. This nesting approach allows multiple functional layers to be integrated within a compact vertical space, achieving high packaging density while maintaining a low profile.
2Quantity of substance
If package-on-package (POP) architecture is used, then packaging density increases, but reliability and cost are worsened
Solution Approach 1:
The patent forms encapsulation material around the vertical interconnects and stacked dies during the manufacturing process, creating protective structures before the package is completed. This preliminary encapsulation protects the interconnects from mechanical stress and environmental factors, enhancing reliability before the package undergoes subsequent processing and assembly.
Solution Approach 2:
The patent introduces encapsulation material as an intermediary substance that fills the spaces between stacked dies and protects the vertical interconnects. This encapsulation layer acts as a mediator that mechanically supports the stacked structure, isolates it from environmental factors, and reduces stress on the interconnects, thereby improving overall package reliability.
3Ease of operation
If vertical interconnects are exposed, then connectivity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent selectively removes portions of the encapsulation material to create rounded cavities that expose the vertical interconnects at the package surface. This extraction approach maintains the protective encapsulation for most of the structure while creating localized access points for the interconnects, balancing connectivity requirements with manufacturing simplicity.
Solution Approach 2:
The patent forms rounded cavities with curved surfaces instead of sharp or angular features. This curvature simplifies the manufacturing process by allowing the use of spherical or hemispherical masking structures during fabrication, and it reduces stress concentration points that could lead to reliability issues, thereby lowering overall manufacturing complexity while maintaining interconnect exposure.
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system includes: providing a substrate; attaching an integrated circuit to the substrate; attaching a vertical interconnect over the substrate; forming an encapsulation on the substrate and covering the vertical interconnect; and forming a rounded cavity, having a curved side, in the encapsulation with the vertical interconnect exposed in the rounded cavity.