Vertical Interconnect Structure for 3-D FO-WLCSP
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Solution Overview
Problem
Current methods for forming vertical electrical interconnections in semiconductor packages, such as through silicon vias (TSVs) and through hole vias (THVs), are time-consuming, costly, and prone to defects due to void formation, and face challenges with die placement accuracy and warpage control.
Innovation Solution
A method involving the formation of conductive pillars and redistribution layers (RDLs) over a substrate, with a semiconductor die disposed adjacent to the pillars, and the use of solder bumps for interconnects, to create a vertical interconnect structure for 3-D fan-out wafer level chip scale packages (FO-WLCSPs).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through silicon vias (TSVs) or through hole vias (THVs) are used for vertical interconnections, then electrical connectivity between multiple levels is achieved, but manufacturing time increases and production efficiency decreases
Solution Approach 1:
Conductive pillars are formed on the carrier substrate before semiconductor dies are mounted. This preliminary formation of interconnect structures allows subsequent die attachment and wire bonding to proceed without interrupting the interconnect formation process, thereby reducing total manufacturing time while ensuring reliable electrical connectivity.
Solution Approach 2:
The patent combines multiple manufacturing operations into a single integrated process flow. Conductive pillar formation, die mounting, wire bonding, and encapsulation are performed in sequence without removing the wafer from the carrier, merging what would traditionally be separate batch processes into one continuous operation that improves productivity while maintaining connectivity reliability.
2Strength
If conformal plating of sidewalls and bottom-side of vias is performed, then adhesion is enhanced, but manufacturing cost increases due to additional equipment and process complexity
Solution Approach 1:
The patent extracts the adhesion function from the complex conformal plating process by using conductive paste applied directly to the carrier substrate. This simplified approach achieves the necessary adhesion for conductive pillars without requiring the expensive electroplating equipment and multi-step conformal plating processes, thereby reducing manufacturing cost while maintaining adequate bond strength.
3Quantity of substance
If electroplating process is used for via filling, then conductive material is deposited, but manufacturing time increases and unit-per-hour production schedule is reduced
Solution Approach 1:
The patent uses conductive paste as a disposable, pre-formed material for creating conductive pillars, replacing the time-consuming electroplating process. The paste is applied, patterned, and cured in a single sequence that takes a fraction of the time required for electroplating, thereby maintaining adequate conductive material deposition while dramatically improving unit-per-hour production schedule.
4Reliability
If TSVs or THVs are used for vertical interconnections, then electrical connectivity is established, but die placement accuracy and warpage control become problematic
Solution Approach 1:
Conductive pillars are formed and positioned on the carrier substrate before die mounting. This preliminary positioning establishes precise registration points that guide die placement, ensuring accurate alignment of bond pads with conductive pillars. The carrier substrate acts as a stable reference plane that minimizes warpage during subsequent processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing time and cost, enhances interconnect reliability, and improves die placement accuracy, providing a more efficient and cost-effective method for creating vertical electrical connections in semiconductor packages.
Implementation Method 1
The conductive layer (104) electrically connects the conductive pillar (110) to external devices
Implementation Method 2
an electrically conductive solder material is deposited over the conductive layer (104)... to form a solder bump (152)
Data Source
AI summary
A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed.