Vertical Interconnect Packaging for Thick-Die Thermal Performance
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Solution Overview
Problem
Existing electronic packages and manufacturing methods are inadequate, leading to excess cost, decreased reliability, and relatively low performance with large package sizes.
Innovation Solution
The use of tall and narrow vertical interconnect structures between upper and lower substrates, incorporating conductive bodies such as copper core balls and wires, to support a thick-cavity interposer, which allows for increased die thickness and improved thermal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional electronic packages are used, then manufacturing is simpler, but reliability decreases and performance is reduced
Solution Approach 1:
The package is divided into multiple substrates (first substrate, second substrate, intermediate substrate) with distinct functional layers. Each substrate can be manufactured and tested independently, then assembled together, improving overall reliability while managing complexity through modular construction
Solution Approach 2:
The patent implements a nested structure where the intermediate substrate is positioned between the first and second substrates, creating a layered configuration. The encapsulant material is nested around the vertical interconnect structures and electronic components, providing protection while maintaining a compact hierarchical arrangement that enhances reliability
2Reliability
If conventional packages are used, then manufacturing cost is lower, but performance is relatively low
Solution Approach 1:
The patent transitions from conventional planar interconnect structures to three-dimensional vertical interconnect structures with height greater than width. This vertical dimension enables shorter signal paths and improved electrical performance while accommodating higher density, achieving superior performance without proportionally increasing manufacturing difficulty
Solution Approach 2:
The patent changes the geometric parameters of interconnect structures by establishing that height is greater than width, creating tall narrow vertical structures. This parameter change optimizes electrical performance and thermal management while the standardized manufacturing process for these structures maintains ease of production
3Temperature
If die thickness is increased for better thermal performance, then thermal performance improves, but package size increases
Solution Approach 1:
The patent applies different material properties and structural characteristics to different regions of the package. The intermediate substrate and encapsulant materials are specifically selected and configured to provide enhanced thermal management in critical areas, allowing thick dies to be used for thermal performance without proportionally increasing overall package volume
Solution Approach 2:
The encapsulant material is nested around the vertical interconnect structures and electronic components in a space-efficient configuration. This nested arrangement protects the thick dies and vertical structures while minimizing the external package dimensions, achieving compact size despite increased die thickness for thermal performance
4Manufacturing precision
If pitch density is reduced, then manufacturing precision requirements decrease, but device performance may be affected
Solution Approach 1:
The patent moves interconnect structures into the vertical dimension, creating tall narrow structures that extend perpendicular to the substrate planes. This vertical arrangement reduces the horizontal pitch density requirements while maintaining electrical performance, as the vertical height provides the necessary interconnect length without increasing lateral spacing
Solution Approach 2:
The patent fundamentally changes the interconnect geometry by making height greater than width, creating vertical structures rather than horizontal traces. This parameter change allows for reduced pitch density in the manufacturing process while maintaining or improving device performance through the optimized vertical interconnect path
Data Source
AI summary
In one example, an electronic device includes a first substrate, an electronic component coupled to a side of the first substrate, and a vertical interconnect structure coupled to the side of the first substrate. The vertical interconnect structure includes a first interconnect structure coupled to the side of the first substrate, and an intermediate substrate having a first side coupled to the first interconnect structure. The intermediate substrate comprises inner sidewalls defining a cavity with the electronic component extending through the cavity. A second interconnect structure can be coupled to a second side of the intermediate substrate opposite the first side of the intermediate substrate. An encapsulant can be disposed over the first substrate and the intermediate substrate, around the electronic component, around the first interconnect structure, around the second interconnect structure, and around the intermediate substrate. Other examples and related methods are also disclosed herein.