Vertical Interconnects for Buried Capacitance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing decoupling capacitors in semiconductor devices consume significant chip area and are limited by fin and gate patterning, leading to inefficiencies in capacitance per unit area and risk of breakdown, while back-end-of-line capacitors waste routing resources and are prone to size-related issues.
Innovation Solution
The method involves forming a multi-level interconnect structure with alternating layers of semiconductor and conductive materials, using block materials to define specific contact points for vertical metallization, creating self-contained capacitors that do not waste FEOL area or routing resources, allowing for scalable performance and reduced series resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional decoupling capacitors are used in semiconductor devices, then capacitance function is provided, but significant chip area is consumed
Solution Approach 1:
The patent transitions from planar capacitor layouts to vertical three-dimensional structures by forming alternating conductive and dielectric material layers in the vertical dimension. This enables capacitance to be stacked vertically beneath FET channels, dramatically increasing capacitance density while minimizing lateral chip area consumption.
Solution Approach 2:
The capacitor structure is nested within the device footprint by placing alternating conductive and dielectric layers in the vertical space beneath the FET channel, effectively utilizing the volume under existing device structures rather than consuming additional lateral chip area.
2Ease of manufacture
If fin and gate patterning is used for capacitor formation, then capacitor structure is created, but manufacturing complexity increases and area efficiency decreases
Solution Approach 1:
The capacitor is segmented into multiple thin alternating layers of conductive and dielectric materials deposited sequentially. This layered segmentation enables precise control of capacitance values and allows standard thin-film deposition processes to be used, simplifying manufacturing while achieving high capacitance density in vertical stacking.
3Reliability
If back-end-of-line capacitors are used, then decoupling function is provided, but routing resources are wasted and size-related issues arise
Solution Approach 1:
The capacitor structure is merged with the front-end device fabrication process by forming alternating conductive and dielectric layers concurrently with FET structure formation. This integration eliminates the need for separate back-end capacitor fabrication and routing, reducing overall device complexity and routing resource consumption while maintaining reliability.
Data Source
AI summary
A method is presented for forming a multi-level of interconnects underneath a complementary metal oxide semiconductor (CMOS) device. The method includes forming a stack including alternating layers of a semiconductor material and a first conductive material, patterning vias in the stack to define multiple stacks, depositing a first block material within each of the vias, forming a series of first block materials within a first via, forming a series of second block materials within a second via, the first and second vias being on opposed ends of a stack of the multiple stacks, and performing vertical metallization between the first block material and the series of first block materials in the first via, and between the first block material and the series of second block materials in the second via.