Self-Aligned Vertical LDD Sinker Reduces LDMOS Cell Pitch
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Solution Overview
Problem
Conventional LDMOS transistors with backside drain structures have large cell pitch and high on-resistance due to lateral diffusion and misalignment, requiring a more efficient design for reduced size and improved performance.
Innovation Solution
The implementation of self-aligned vertical LDD and sinker regions, stacked vertically between gate electrodes, with the sinker region fully embedded and having a higher dopant concentration than the LDD regions, reduces cell pitch and on-resistance by optimizing dopant distribution and eliminating misalignment provisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If LDD region is extended laterally to obtain high voltage, then breakdown voltage is improved, but device area increases
Solution Approach 1:
The patent transitions from lateral extension of LDD region to vertical stacking of LDD and sinker regions. The LDD region is positioned between the gate electrode and the sinker region in the vertical dimension, allowing high voltage capability to be achieved through vertical dopant distribution rather than lateral area expansion.
Solution Approach 2:
The sinker region is embedded within the semiconductor region and positioned vertically underneath the LDD region. This nested vertical arrangement allows both the LDD region and sinker region to occupy the same lateral footprint while providing the dopant distribution needed for high breakdown voltage without increasing device area.
2Ease of manufacture
If deep diffusion is used to reach backside drain, then drain contact is achieved, but die area is consumed due to side diffusion and misalignment
Solution Approach 1:
The LDD region is formed with self-alignment to the gate electrode, eliminating the need for additional alignment margins. The sinker region is positioned vertically underneath the LDD region, creating a self-aligned vertical structure that reaches the backside drain without requiring lateral misalignment provisions, thereby reducing die area.
Solution Approach 2:
The patent moves from lateral diffusion approaches to vertical diffusion for the sinker region. By stacking the LDD and sinker regions vertically, the structure achieves backside drain contact through vertical positioning rather than lateral extension, reducing the die area consumed by misalignment provisions.
3Ease of manufacture
If conventional lateral arrangement is used, then manufacturing is simple, but cell pitch is large
Solution Approach 1:
The patent transforms the conventional lateral arrangement of source-gate-drain into a vertical stack of LDD and sinker regions between the gate electrode and backside drain. This vertical stacking in the depth dimension reduces the lateral cell pitch while maintaining manufacturing simplicity through self-aligned formation processes.
Solution Approach 2:
The LDD region and sinker region are merged into a vertical stack rather than being arranged laterally. This combination in the vertical dimension allows both regions to function within a compact lateral footprint, reducing cell pitch while maintaining ease of manufacture through integrated formation steps.
4Strength
If lateral LDD extension is used, then high voltage is achieved, but on-resistance is high
Solution Approach 1:
The sinker region with higher dopant concentration is embedded vertically underneath the LDD region. This nested vertical arrangement creates a dopant concentration gradient that reduces on-resistance by providing a low-resistance path through the vertical stack, while the LDD region extends the depletion region vertically to maintain high breakdown voltage capability.
Solution Approach 2:
The patent applies different dopant concentrations at different vertical positions: the LDD region has a lower dopant concentration to extend the depletion region for high voltage, while the sinker region has a higher dopant concentration to reduce on-resistance. This local variation in dopant quality optimizes both high voltage capability and low on-resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a smaller cell pitch, lower on-resistance, and improved transistor performance with reduced manufacturing complexity and cost, while maintaining high breakdown voltage.
Implementation Method 1
The sinker region is disposed in the semiconductor region directly underneath the at least one LDD region such that the at least one LDD region and the sinker region are positioned along a vertical orientation
Data Source
AI summary
A field effect transistor includes a semiconductor region of a first conductivity type having an upper surface and a lower surface, the lower surface of the semiconductor region extending over and abutting a substrate. A well regions of a second conductivity type is disposed within the semiconductor region. The field effect transistor also includes source regions of the first conductivity type disposed in the well regions and a gate electrode extending over each well region and overlapping a corresponding one of the source regions. Each gate electrode is insulated from the underlying well region by a gate dielectric. At least one LDD region of the first conductivity type is disposed in the semiconductor region between every two adjacent well regions such that the at least one LDD region is in contact with the two adjacent well regions between which it is disposed. A sinker region is disposed in the semiconductor region directly underneath the at least one LDD region such that the at least one LDD region and the sinker region are positioned along a vertical orientation between the upper and lower surfaces of the semiconductor region.