Vertical LED Die Isolation Using an Insulation Implant Layer
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Solution Overview
Problem
The existing manufacturing process for vertical-type LEDs faces challenges in achieving small spacing between dies due to high aspect ratios, leading to electrode breakage and uneven surfaces, which affects the photoelectric quality, as conventional methods like PI adhesive fail to address the height differences effectively under high temperatures.
Innovation Solution
The formation of an insulation implant layer through ion implantation in the semiconductor stack layer, which divides the semiconductor stack into individual dies without the need for trenches or PI adhesive, ensuring insulation and a flat surface by using materials like hydrogen, argon, nitrogen, or helium atoms, thereby maintaining a height difference of less than 0.5 μm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If PI adhesive is used to fill the spacing between dies, then the height difference problem is temporarily solved, but the adhesive damages under high temperature during annealing treatment, causing surface unevenness and electrode breakage
Solution Approach 1:
The patent removes the PI adhesive layer entirely and replaces it with a direct semiconductor structure. The n-type GaN layer serves as both the semiconductor active layer and the insulation layer, eliminating the need for organic adhesives that cannot withstand high-temperature annealing processes.
Solution Approach 2:
The patent changes the material parameter from organic PI adhesive to inorganic n-type GaN semiconductor material, which can withstand high temperatures. This parameter change enables the structure to maintain surface flatness and electrode integrity during annealing treatment at elevated temperatures.
2Reliability
If dry etching is performed to create trenches for insulation, then die isolation is achieved, but the high aspect ratio causes climbing behavior of transparent electrodes and leads to ITO breakage
Solution Approach 1:
The patent eliminates the trench structure created by dry etching and replaces it with a planar semiconductor layer approach. The n-type GaN layer is grown directly to cover the entire surface, providing insulation without requiring deep trenches that create high aspect ratios and electrode climbing issues.
Solution Approach 2:
Instead of creating trenches to go down into the substrate for insulation, the patent inverts the approach by growing an insulation layer from the top surface downward in terms of functional layering, but maintaining a planar top surface that prevents electrode climbing.
3Measurement precision
If the spacing between dies is reduced to less than 5 μm, then higher resolution is achieved, but the high aspect ratio makes dry etching difficult and causes manufacturing defects
Solution Approach 1:
The patent removes the dry etching step entirely and replaces it with a semiconductor layer growth process. By using epitaxial growth to form the n-type GaN insulation layer, the method avoids the difficulties of dry etching high-aspect-ratio trenches at sub-5 μm spacing.
Solution Approach 2:
The patent replaces the mechanical/chemical removal process of dry etching with a deposition/growth process of epitaxial semiconductor layer formation. This substitution enables precise control at sub-5 μm spacing without the limitations of etching physics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for small spacing between dies while maintaining insulation and achieving a flat surface, enhancing the photoelectric quality of vertical-type light-emitting diodes by preventing electrode breakage and ensuring a stable connection.
Implementation Method 1
the insulation implant layer is directly formed in the semiconductor stack layer by means of ion implantation
Data Source
AI summary
The disclosure relates to the field of semiconductor manufacturing technology, and in particular to a vertical-type light-emitting diode, which includes a substrate, a semiconductor stack layer and an insulation implant layer. The semiconductor stack layer is disposed on the substrate, and the semiconductor stack layer includes the first semiconductor layer, the light-emitting layer and the second semiconductor layer that are sequentially stacked on the substrate. The insulation implant layer is formed in the semiconductor stack layer to divide the semiconductor stack layer into at least two individual dies. By forming the insulation implant layer in the semiconductor stack layer, it is possible to achieve small spacing between dies and allow them to be insulated from each other without the need to create trenches or use PI adhesive. It is possible to ensure the photoelectric quality of the vertical-type light-emitting diodes and make the surface of the vertical-type light-emitting diodes flatter.