Vertical Memory Interconnect for Signal Integrity

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current memory interconnect arrangements in computer systems face challenges with data transfer speed and signal integrity, particularly when trying to fit multiple DIMMs per channel in a BGA 2011 quad socket implementation, as they often lack sufficient space and result in inadequate signal integrity for high-speed data transfers like 1866 mega transfers per second.

Innovation Solution

The proposed solution involves a motherboard configuration with a processor mounted on a surface, a memory card printed circuit board with perpendicular slots, and right angle backplane connectors that connect the memory cards in a vertical stacked arrangement, allowing for 32 DIMM slots and 4 BGA 2011 CPU sockets in a 2U tall rack space, using full height DDR3 memory modules and minimizing trace length to enhance signal integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If vertically extending memory board is plugged into edge card connector to reduce surface space, then area occupied by CPUs and memory cards is reduced, but data transfer speed and signal integrity deteriorate

Engineering Contradiction:
Improvesurface space occupied by CPUs and memory cardsVSAvoidsignal integrity and data transfer speed
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent transitions from a horizontal edge connector layout to a vertical backplane connector arrangement. Memory cards are stacked vertically and connected through the backplane, utilizing the vertical dimension to reduce surface area while maintaining signal integrity through optimized trace routing and shorter connector lengths.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The memory system is segmented into multiple vertical stacks, each with its own backplane connector. This segmentation allows for shorter trace lengths within each stack, improving signal integrity while accommodating multiple DIMMs per channel in a compact footprint.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If multiple DIMMs per channel are fitted in BGA 2011 quad socket implementation, then memory capacity is increased, but board real estate and routing limitations prevent sufficient room for implementation

Engineering Contradiction:
Improvenumber of DIMMs per channelVSAvoidboard real estate
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent uses vertical stacking of memory cards connected through backplane connectors, transforming the horizontal board layout into a vertical three-dimensional arrangement. This enables fitting 32 DIMM slots in a 2U rack space by utilizing vertical space rather than horizontal board area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

Multiple memory cards are nested vertically in stacked arrangements, with each card plugged into memory board slot type connectors on a vertically extending memory board. This nesting approach maximizes the number of DIMMs per channel within the available vertical space.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Area of stationary object

If edge connector is used to connect vertically extending memory board, then surface space is reduced, but data transfer speed and signal integrity become insufficient for high-speed transfers

Engineering Contradiction:
Improvesurface spaceVSAvoiddata transfer speed
Core Design Contradiction:
Area of stationary objectVSSpeed

Solution Approach 1:

The patent changes key parameters including connector type (from edge connector to right angle backplane connector), trace length (shortened), and connector orientation (vertical). These parameter changes enable support for high-speed transfers of 1866 mega transfers per second while maintaining compact form factor.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9155194B1Memory interconnect arrangement having high data transfer speed signal integrity
Publication Date: 2015.10.06 EMC IP HLDG CO LLC
  • US9155194B1 patent drawing
  • US9155194B1 patent drawing
  • US9155194B1 patent drawing

AI summary

An arrangement having a processor electrically to, and mounted on, a portion of a surface of a motherboard. A plurality of memory cards is plugged into memory board slot type connectors on a surface of the memory card printed circuit board with the surface of the memory card printed circuit board being perpendicular to the surface of the motherboard. A right angle backplane connector has a first end disposed perpendicular to, and electrically connected to the surface of a motherboard and a second end disposed on the surface of, and electrically connected to, the memory card printed circuit board. The plurality of memory cards is parallel to the surface of the motherboard. An ejector mechanism is provided for removing the memory printed circuit board from an electrical connector receptacle mounted to the motherboard by camming action.