Vertical Charge-Trap Memory Cell for Bit-Level Erase Control
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Solution Overview
Problem
Conventional charge trapping memories have a large surface footprint and lack granular control for both programming and deletion operations, requiring a significant number of manufacturing steps and resulting in high production costs.
Innovation Solution
A non-volatile memory device with a vertically buried control gate and dielectric interface in a semiconductor substrate, featuring a vertical implanted region of opposite dopant type, allowing for selective and granular programming and deletion operations with reduced surface area and manufacturing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional planar transistor structure is used, then manufacturing is simpler, but surface footprint is larger
Solution Approach 1:
The patent transitions from a planar (2D) transistor structure to a vertical (3D) structure where the control gate is buried vertically in the substrate. This dimensional change allows the memory cell to occupy significantly less surface area while maintaining the essential transistor functionality, directly resolving the contradiction between manufacturing simplicity and surface footprint reduction.
2Ease of operation
If Fowler-Nordheim effect controlled deletion is used, then deletion operation is achieved, but granularity is limited to row level
Solution Approach 1:
The patent segments the deletion operation capability by introducing vertically implanted regions that can be independently controlled. This segmentation allows deletion to be applied selectively to individual memory cells or specific groups, rather than requiring row-level operations, thereby achieving bit-level or finer granularity while maintaining deletion functionality.
Solution Approach 2:
The vertically implanted regions provide localized charge carrier injection capability at specific positions within the substrate. This local quality enhancement enables selective deletion operations on individual memory cells or small groups, improving granularity from row-level to bit-level while preserving the deletion operation capability through controlled carrier injection in specific regions.
3Reliability
If conventional charge trapping memory is used, then charge storage is achieved, but surface footprint is not reduced
Solution Approach 1:
The patent maintains the charge trapping functionality by preserving the dielectric interface structure while transitioning to a vertical configuration. The control gate is buried vertically and the dielectric interface covers the sides of the control gate, enabling charge storage in a compact vertical arrangement that significantly reduces surface footprint compared to conventional planar structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables compact memory cells with bit-level granularity for both writing and deletion, reducing production costs and improving surface efficiency while maintaining selectivity and accessibility of multiple bits per cell.
Implementation Method 1
a dielectric interface able to trap electrical charges covering the sides of the control gate facing the semiconductor substrate
Implementation Method 2
a vertical implanted region of a second type of dopant opposite to the first type, for example n-type, located along said sides of the control gate in the semiconductor substrate
Implementation Method 3
allowing for selective programming and deletion at the bit level through the injection of hot charge carriers
Data Source
AI summary
The non-volatile memory device includes memory cells including a control gate vertically buried in a semiconductor substrate doped with a first type of dopant and a dielectric interface able to trap electrical charges covering sides of the control gate facing the semiconductor substrate. The device furthermore includes a vertical implanted region of a second type of dopant opposite to the first type located along the sides of the control gate in the semiconductor substrate.