Vertical Charge-Trap Memory for Bit-Level Erase and High Density
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Solution Overview
Problem
Conventional charge trap memories lack compactness and granularity in writing and erasing operations, with erasure typically occurring at a page level rather than a bit level, and have a high manufacturing footprint.
Innovation Solution
A non-volatile memory device with a vertically buried control gate and dielectric interface in a semiconductor substrate, featuring a vertical implanted region of opposite dopants, allowing for selective erasure and programming at a bit level without channel inversion, and enabling storage of two independent bits per memory cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a conventional planar transistor structure is used, then the manufacturing process is simple, but the surface area occupied by each memory cell is large
Solution Approach 1:
The patent transitions from a conventional planar (2D) transistor structure to a vertical (3D) structure where the control gate is buried vertically in the substrate. This dimensional change allows multiple memory cells to be stacked in the vertical direction, significantly reducing the surface footprint per cell while maintaining manufacturability through standard semiconductor processing techniques adapted for vertical geometries.
Solution Approach 2:
The control gate is nested vertically within the substrate, with the dielectric interface wrapping around the gate structure. This nested configuration allows the memory cell components to be packed more efficiently in three dimensions, reducing the horizontal surface area required for each cell while preserving all necessary functional elements.
2Reliability
If Fowler-Nordheim effect is used for erasure, then erasure can be achieved, but the granularity is limited to page level rather than bit level
Solution Approach 1:
The patent introduces vertically implanted doped regions that are spatially segmented and positioned to enable selective activation of individual memory cells or small groups of cells. This segmentation allows the erasure operation to be applied with bit-level or fine-grained selectivity rather than requiring page-level-wide erasure, giving precise control over which cells are erased.
Solution Approach 2:
The vertically implanted doped regions provide locally enhanced electrical fields and charge carrier generation that can be selectively activated. This local quality enhancement enables targeted erasure operations on specific bits or small groups of bits without affecting other cells, achieving fine granularity control while maintaining reliable erasure functionality.
3Manufacturing precision
If conventional charge trapping structure is used, then programming with one-bit granularity is achieved, but erasure requires larger granularity
Solution Approach 1:
The vertically implanted doped regions are segmented and positioned to match the bit-level structure of the memory array. This segmentation enables both programming and erasure operations to be applied with the same fine granularity, allowing selective manipulation of individual bits or small groups of bits for both write and erase operations.
Solution Approach 2:
The patent changes the electrical parameters (doping type, implantation depth, concentration) of the vertically implanted regions to optimize both programming and erasure operations. By carefully controlling these parameters, the structure enables symmetric bit-level control for both programming and erasure, eliminating the granularity mismatch present in conventional structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the surface area occupied by each memory cell, allows for selective erasure and programming of individual bits, and enables access to four bits with a single control gate structure, enhancing storage density and selectivity.
Implementation Method 1
a dielectric interface capable of trapping electric charges covering flanks of the control gate opposite the semiconductor substrate
Implementation Method 2
a vertical implanted region of a second type of dopant opposite the first type, for example the N type, located along said flanks of the control gate in the semiconductor substrate
Data Source
Figure 1~3
Figure 4~5
Figure 6A~6B
AI summary
The non-volatile memory device comprises memory cells (CEL1, CEL2) with a control gate (CG) vertically embedded in a semiconductor substrate (SUB) doped with a first type of dopant, and a dielectric interface (ITFD) capable of trapping electrical charges covering the flanks (FL1, FL2) of the control gate (CG) facing the semiconductor substrate. The device further comprises a vertically embedded region (AdVt) of a second type of dopant, opposite to the first type, located along said flanks of the control gate (FL1, FL2) in the semiconductor substrate (SUB).