Vertical Memory Structure With C-Shaped Cross-Section
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high memory density and large storage capacity while maintaining a small size, as traditional methods do not effectively utilize vertical memory structures to maximize storage capacity in a compact form factor.
Innovation Solution
The semiconductor structure features interlaced conductive and insulating layers with vertically stacked memory structures having horizontal C-shaped cross-sections, separated by an isolation trench, which increases memory density and storage capacity by allowing for simultaneous program/erase operations and improved processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional memory device structures are used, then the device size remains compact, but the memory density and storage capacity are limited
Solution Approach 1:
The patent transitions from planar memory structures to three-dimensional vertical memory structures. Multiple memory layers are stacked vertically with conductive layers and insulating layers interleaved, creating a multi-layered architecture that increases memory density by utilizing the vertical dimension rather than expanding horizontally.
Solution Approach 2:
The patent implements a nested structure where vertical memory structures are embedded within a substrate, with conductive layers and insulating layers interleaved and stacked around the vertical memory structures. The isolation trench further nests within the structure to separate adjacent vertical memory structures, creating a compact hierarchical arrangement that maximizes space utilization.
2Quantity of substance
If vertical memory structures are implemented to increase memory density, then storage capacity improves, but manufacturing complexity increases
Solution Approach 1:
The patent divides the memory device into discrete vertical memory structures that are separated by isolation trenches. Each vertical memory structure can be independently formed and processed, allowing for modular manufacturing. The interleaved conductive and insulating layers are also segmented into distinct alternating layers, simplifying the fabrication process by breaking down the complex three-dimensional structure into manageable sequential deposition steps.
3Quantity of substance
If isolation trench is added to separate vertical memory structures, then memory density increases, but device complexity increases
Solution Approach 1:
The patent extracts the isolation function into a separate isolation trench that is formed between vertical memory structures. This isolation trench is filled with insulating material and serves to electrically isolate adjacent vertical memory structures, preventing unwanted electrical interactions. By separating the isolation function from the memory structure itself, the design achieves higher memory density while maintaining manageable structural complexity through functional decomposition.
Data Source
AI summary
A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a plurality of conductive layers, a plurality of insulating layers, a first vertical memory structure, a second vertical memory structure, and an isolation trench. The conductive layers and the insulating layers are interlaced and stacked on the substrate. The first vertical memory structure and the second memory structure penetrate the conductive layers and the insulating layers are formed on the substrate. The first vertical memory structure has a first horizontal C shaped cross-section, and the second vertical memory structure has a second horizontal C shaped cross-section. The isolation trench is formed between the first vertical memory structure and the second vertical memory structure.