Vertical Memory Cell With Capacitor Element For Data Retention
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Solution Overview
Problem
Existing memory devices face challenges in achieving high reliability, large storage capacity, small area occupation, high memory density, and low manufacturing costs, primarily due to trap centers at the semiconductor-insulator interface that affect threshold voltage and data retention.
Innovation Solution
The memory device incorporates n memory cells, each with a first and second transistor, and a capacitor element connected to the third conductive layer of the second transistor, which enhances data retention and stability by providing a region where the transistors overlap, thus improving electrical connections and reducing contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked to increase storage capacity, then storage capacity per unit area is improved, but trap centers are formed at the semiconductor-insulator interface that shift threshold voltage and reduce reliability
Solution Approach 1:
The patent introduces an intermediary structure (the insulating layer with the charge storage layer positioned between the semiconductor pattern and the conductive layer) that mediates the interaction between the semiconductor and insulator. This intermediary structure allows charge storage while preventing direct contact that would generate trap centers, thus maintaining both high storage capacity through stacking and high reliability through reduced interface defects.
2Quantity of substance
If semiconductor pattern is in direct contact with insulator for charge storage, then charge storage function is achieved, but trap centers are generated at the interface that adversely affect transistor threshold voltage
Solution Approach 1:
The patent segments the interface between the semiconductor pattern and the charge storage insulator by introducing an intermediate insulating layer. This segmentation separates the charge storage function (in the insulating layer) from the semiconductor contact region, preventing trap center formation at the semiconductor-insulator interface while maintaining charge storage capability through the segmented structure.
3Quantity of substance
If multiple memory cells are stacked in series to form three-dimensional array, then storage capacity per unit area is increased, but manufacturing complexity increases
Solution Approach 1:
The patent applies the nesting principle by stacking multiple memory cells (each containing transistors and charge storage structures) in a three-dimensional array configuration. Each memory cell is nested within the vertical structure, with conductive layers and insulating layers arranged in concentric stacks, enabling high storage capacity per unit area while using standardized repeating units that simplify manufacturing through process reuse.
Data Source
AI summary
A novel memory device is provided. A plurality of memory cells each including two vertical transistors are connected in series. One of the two transistors functions as a transistor for writing data, and the other functions as a transistor for reading the data that has been written to the memory cell. Data written to the memory cell is retained in a gate of the reading transistor. A transistor with low off-state current is used as the writing transistor.