Vertical Memory Cell Integration via Charge Blocking Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional two-dimensional semiconductor memory devices face limitations in increasing integration density due to high costs of micro-patterning equipment and charge leakage issues in vertically stacked non-volatile memory devices.
Innovation Solution
A non-volatile memory device with a substrate of single crystalline semiconductor, featuring pillar-shaped semiconductor patterns, alternately stacked gate electrodes, interlayer dielectric layers, and a charge spread blocking layer to prevent charge leakage and enhance reliability, allowing for vertical stacking of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional two-dimensional semiconductor memory device structure is used, then manufacturing process is simpler, but integration density cannot be increased sufficiently
Solution Approach 1:
The patent transitions from a conventional two-dimensional planar structure to a three-dimensional vertical structure by stacking multiple gate electrodes, charge storage layers, and interlayer dielectric layers vertically. This vertical stacking enables increased integration density without requiring further reduction in lateral dimensions, effectively utilizing the third dimension to accommodate more memory cells per unit area.
2Manufacturing precision
If vertically stacked non-volatile memory device is used, then integration density is improved, but charge leakage occurs in charge storage layer
Solution Approach 1:
The patent introduces a charge spread blocking layer as an intermediary component positioned between adjacent gate electrodes and charge storage layers. This blocking layer acts as a mediator that prevents charge leakage and electrical interference between neighboring vertical memory cell strings, thereby improving charge retention reliability while maintaining the high integration density benefits of the vertical stacking structure.
3Manufacturing precision
If micro-patterning technology is advanced to increase integration density, then more memory cells can be packed, but equipment cost increases significantly
Solution Approach 1:
The patent adopts a vertical stacking architecture that grows memory cells in the vertical direction rather than packing them horizontally. This approach allows integration density to be increased through the third dimension (stack height) rather than requiring continuous advancement of lateral micro-patterning capabilities, thereby reducing dependence on expensive cutting-edge lithography equipment.
Solution Approach 2:
The patent divides the memory device into multiple identical vertical cell strings stacked in parallel. Each vertical string contains multiple memory cells formed by repeating the same layer structure (gate electrode, charge storage layer, interlayer dielectric layer). This segmentation into modular repeating units simplifies the manufacturing process, as the same fabrication steps can be applied repeatedly to create multiple cells without requiring increasingly complex single-step patterning.
Data Source
AI summary
A non-volatile memory device is provided, including a substrate formed of a single crystalline semiconductor, pillar-shaped semiconductor patterns extending perpendicular to the substrate, a plurality of gate electrodes and a plurality of interlayer dielectric layers alternately stacked perpendicular to the substrate, and a charge spread blocking layer formed between the plurality of gate electrodes and the plurality of interlayer dielectric layers.