Vertical Memory Cell Junction Area Reduction
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Solution Overview
Problem
As semiconductor memory devices are scaled down, the volume of the electrically floating body region in vertical memory cells decreases, leading to increased charge leakage across capacitance paths, which affects data retention and performance.
Innovation Solution
The solution involves reducing the junction cross-sectional areas relative to the body region by modifying the dimensions and volumes of the semiconductor structure, specifically through etching and oxidation processes, to minimize charge leakage while maintaining a sufficient volume for charge storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the volume of the electrically floating body region is increased to store more electrical charge, then the data storage capacity is improved, but the device area and complexity increase
Solution Approach 1:
The patent transitions from planar memory structures to vertical memory cell structures, utilizing the third dimension (depth) to increase charge storage capacity. The electrically floating body region is extended vertically beneath control gates, allowing greater volume and charge storage without increasing the lateral footprint of the device, thus resolving the contradiction between storage capacity and device complexity.
2Productivity
If the volume of the electrically floating body region is reduced through scaling, then the device density is improved, but charge leakage across junctions increases
Solution Approach 1:
The patent applies different doping concentrations and material properties to specific regions of the vertical memory cell. The electrically floating body region is carefully doped to balance charge storage capability with reduced leakage, while junction regions are engineered with specific properties to minimize capacitance leakage paths. This localized optimization allows scaling while maintaining charge retention.
Solution Approach 2:
The patent modifies physical parameters such as junction cross-sectional area, doping concentrations, and material compositions to reduce capacitance leakage. By changing these parameters during the scaling process, the device maintains adequate charge storage volume while minimizing leakage paths, thus resolving the contradiction between density and charge leakage.
3Reliability
If the junction cross-sectional area is reduced to minimize capacitance leakage, then charge retention is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary actions during fabrication, such as forming etch-protective materials on sidewalls before etching junction regions. This protective layer is deposited in advance to prevent over-etching and ensure precise junction dimensions. By preparing these protective structures beforehand, the manufacturing process achieves the required precision for reduced junction areas without excessive complexity.
Solution Approach 2:
The patent introduces etch-protective materials as intermediary layers during the fabrication process. These protective materials serve as mediators between the etching process and the semiconductor structures, allowing precise control of junction dimensions. The protective layers are selectively removed after serving their protective function, enabling accurate junction formation with reduced cross-sectional areas while maintaining manufacturability.
Data Source
AI summary
Methods of forming, devices, and apparatus associated with a vertical memory cell are provided. One example method of forming a vertical memory cell can include forming a semiconductor structure over a conductor line. The semiconductor structure can have a first region that includes a first junction between first and second doped materials. An etch-protective material is formed on a first pair of sidewalls of the semiconductor structure above the first region. A volume of the first region is reduced relative to a body region of the semiconductor structure in a first dimension.