Vertical Memory Cell with Semiconductor and Resistance Change Layers
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Solution Overview
Problem
Current nonvolatile memory devices face challenges in achieving high integration density and low power consumption while maintaining efficient random access to memory cells, particularly in next-generation neuromorphic computing platforms.
Innovation Solution
The implementation of a vertical stack-type nonvolatile memory device with a semiconductor layer and a resistance change layer, where specific voltage levels are applied to select and non-select memory cells to control current flow, optimizing resistance states for improved read and program operations, and utilizing a parallel connection structure between the semiconductor and resistance change layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a vertical stack-type structure with semiconductor layer and resistance change layer is implemented, then integration density is increased, but device complexity increases
Solution Approach 1:
The patent transitions from planar memory cell arrangement to a vertical stack-type structure, utilizing the third dimension (height) to increase integration density. Multiple memory cells are stacked vertically with semiconductor layers and resistance change layers arranged in layers, allowing higher capacity within the same chip area.
Solution Approach 2:
The patent employs a composite structure combining semiconductor layers with resistance change layers (such as phase change materials or resistive switching materials). This composite approach enables both high integration density and controlled electrical characteristics for reliable memory operation.
2Productivity
If specific voltage levels are applied to control current flow in select and non-select memory cells, then read and program operations are optimized, but power consumption increases
Solution Approach 1:
The patent applies different voltage levels locally to select and non-select memory cells during read and program operations. By controlling the voltage applied to specific regions (selected cells) versus others (non-selected cells), the patent optimizes operation efficiency while managing power consumption through localized electrical control.
Solution Approach 2:
The patent employs periodic voltage pulses for read and program operations, applying voltages in discrete time intervals rather than continuously. This pulsed voltage application optimizes operation efficiency while reducing average power consumption compared to continuous voltage application.
3Stability of the object's composition
If the semiconductor layer and resistance change layer are connected in parallel, then resistance state uniformity is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent merges the semiconductor layer and resistance change layer into a parallel connection structure within each memory cell. This combination enhances resistance state uniformity by providing multiple conduction paths, stabilizing the overall electrical characteristics despite variations in individual layer properties.
Solution Approach 2:
The patent utilizes the parallel connection to change the effective resistance parameters of the memory cell. By combining layers with different resistance characteristics in parallel, the patent achieves more uniform and predictable resistance states, compensating for manufacturing variations through parameter optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the uniformity of resistance states, increases integration density, and reduces power consumption, facilitating efficient read and program operations while preventing ion leakage and operation failures.
Implementation Method 1
resistance change layer
Implementation Method 2
resistance change layer
Implementation Method 3
semiconductor layer
Data Source
AI summary
A nonvolatile memory device and a method of operating the same are provided. The nonvolatile memory device may include a memory cell array having a vertical stack-type structure, a control logic, and a bit line. The memory cell array may include memory cells that each include corresponding portions of a semiconductor layer and a resistance change layer. The control logic, in a read operation, may be configured to apply a first voltage to a non-select memory cell and a second voltage to a non-select memory cell. The first voltage turns on current only in the semiconductor layer portion of the non-select memory cell. The second voltage turns on current in both the semiconductor layer and resistance change layer portions of the select memory cell. The bit line may be configured to apply a read voltage to the select memory cell during the read operation.