Vertical Memory Device Channel Protrusion for Structural Reliability

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Solution Overview

Problem

As the integration of vertical memory devices increases, existing technologies face challenges in maintaining structural and mechanical reliability due to the stacking of gate lines and insulation layers, which can lead to defects and reduced operational reliability.

Innovation Solution

The proposed solution involves a vertical memory device design with a substrate, a channel protruding vertically, and semiconductor patterns that connect the channel to the substrate, along with gate lines and insulation layers alternately stacked, where the channel includes a protrusion and a dielectric layer structure, and semiconductor patterns that are integral and partially buried in the substrate, enhancing mechanical stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the stacked number of gate lines and insulation layers is increased to achieve higher integration, then the degree of integration is improved, but structural and mechanical reliability deteriorates

Engineering Contradiction:
Improvedegree of integrationVSAvoidstructural and mechanical reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent transitions from a planar memory structure to a vertical three-dimensional structure. Memory cells are stacked vertically above the substrate with channels extending in the vertical direction, allowing multiple gate lines to be stacked around the channels at different heights. This vertical stacking enables higher integration density while maintaining structural integrity through the grounded substrate connection.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The memory device is segmented into multiple vertical channels, each surrounded by stacked gate lines and insulation layers. The channel is divided into a channel body extending vertically and a protrusion at the lower portion that contacts the substrate. This segmentation allows independent formation and control of each memory cell stack, improving both integration and reliability.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If conventional planar structures are used with increased stacking, then manufacturing complexity increases, but mechanical stability deteriorates

Engineering Contradiction:
Improvemanufacturing complexityVSAvoidmechanical stability
Core Design Contradiction:
Device complexityVSStability of the object's composition

Solution Approach 1:

The protrusion is formed at the lower portion of the channel body before final assembly, extending in the horizontal direction to contact the substrate. This preliminary structural preparation ensures mechanical stability is built into the foundation of the vertical stack, preventing defects that would arise from attempting to stabilize the structure after stacking is complete.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The vertical channel structure is nested within a configuration where gate lines and insulation layers are alternately stacked around the channel body. The protrusion is nested at the base, connecting the vertical channel to the substrate. This nested arrangement consolidates multiple components into a compact, mechanically stable vertical unit.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS9997534B2Vertical memory devices
Publication Date: 2018.06.12 SAMSUNG ELECTRONICS CO LTD
  • US9997534B2 patent drawing
  • US9997534B2 patent drawing
  • US9997534B2 patent drawing

AI summary

A vertical memory device includes a substrate, a channel on the substrate, extending in a vertical direction with respect to a top surface of the substrate, and including a protrusion at a lower portion of the channel, the protrusion extending in a parallel direction with respect to the top surface of the substrate, a semiconductor pattern connecting the protrusion and the substrate, and gate lines stacked and spaced apart from each other in the vertical direction, the gate lines on the protrusion and the semiconductor pattern and surrounding the channel.