Vertical Memory Charge Trapping Patterns for Retention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The retention characteristic of VNAND flash memory devices is deteriorated due to charge trapping layers extending vertically along gate electrodes, leading to reliability issues in data storage and retrieval.
Innovation Solution
A vertical memory device design featuring a charge storage structure with a tunnel insulation layer, charge trapping patterns, and a first blocking pattern sequentially stacked on the substrate, along with gate electrodes and an insulation pattern with an air gap, where the charge trapping patterns are spaced apart and each faces a gate electrode, and a protection layer covers the gate electrodes' end portions, enhancing the insulation pattern's thickness and reducing charge movement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a charge trapping layer extends vertically along gate electrodes in VNAND flash memory, then the memory device can store charge, but the retention characteristic deteriorates due to charge movement between gate electrodes at different levels
Solution Approach 1:
The charge trapping layer is divided into multiple separated charge trapping patterns along the vertical direction, with insulation patterns positioned between adjacent charge trapping patterns. This segmentation prevents charge movement between different vertical levels while maintaining charge storage capability at each level.
Solution Approach 2:
Insulation patterns are introduced as intermediary elements between adjacent charge trapping patterns. These insulation patterns act as barriers that block charge movement between different gate electrode levels, thereby improving retention characteristics without eliminating the charge trapping function.
2Reliability
If insulation pattern thickness is increased to prevent charge movement, then retention characteristic improves, but device complexity and manufacturing difficulty increase
Solution Approach 1:
Insulation patterns are selectively positioned only at critical locations where charge movement between adjacent charge trapping patterns occurs. This localized approach provides effective charge isolation without requiring uniform thick insulation throughout the entire device, thereby reducing overall device complexity.
Solution Approach 2:
The charge trapping structure transitions from a continuous vertical layer to discrete patterns arranged in a three-dimensional configuration with insulation patterns positioned in the horizontal direction between them. This dimensional reorganization enables effective charge isolation while maintaining a compact structure.
3Reliability
If charge trapping patterns are spaced apart vertically, then charge movement between gate electrodes is reduced, but the amount of storable charge decreases
Solution Approach 1:
The charge trapping function is segmented into multiple discrete patterns distributed vertically, with each pattern capable of storing charge independently. The segmentation is optimized to provide sufficient spacing for charge isolation while maintaining adequate charge storage capacity across all patterns collectively.
Solution Approach 2:
The memory structure employs a composite arrangement combining charge trapping patterns made of charge-storing material with insulation patterns made of dielectric material. This composite structure enables simultaneous achievement of charge isolation and charge storage by leveraging the complementary properties of different materials.
Data Source
AI summary
A vertical memory device includes a channel extending vertically on a substrate. A charge storage structure is disposed on a sidewall of the channel. Gate electrodes are spaced apart from each other vertically and surround the charge storage structure. A first insulation pattern includes an air gap between the gate electrodes. The charge storage structure includes a tunnel insulation layer, a charge trapping pattern, and a first blocking pattern sequentially stacked horizontally. The charge storage structure includes charge trapping patterns spaced apart from each other vertically. Each of the charge trapping patterns faces one of the gate electrodes horizontally. A length in the first direction of an outer sidewall of each of the charge trapping patterns facing the first blocking pattern is less than that of an inner sidewall thereof facing the tunnel insulation layer.