Vertical Memory Contact Plug Layout for Dense 3D Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in increasing data storage capacity, particularly in efficiently integrating circuit interconnection structures and vertical memory structures to enhance data storage capabilities.
Innovation Solution
A semiconductor device design featuring a lower structure with circuit interconnection patterns at different height levels, a vertical memory structure penetrating through wordlines, and a contact plug connecting bitlines and wordlines, with a layered insulating structure to prevent defects and improve integration, using materials like silicon nitride and silicon oxide for insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical memory structures are used to increase storage capacity, then data storage capacity is improved, but device complexity increases due to integration of multiple structures at different height levels
Solution Approach 1:
The device is divided into distinct lower and upper structures with separate functions. The lower structure contains circuit devices and interconnection patterns, while the upper structure contains vertical memory structures and wordlines. This segmentation allows independent optimization of each subsystem while reducing overall integration complexity.
Solution Approach 2:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertical memory structures. The vertical memory structures extend in the vertical direction through multiple wordlines, enabling increased storage capacity by utilizing the third dimension rather than only expanding in the planar direction.
2Reliability
If contact plugs are used to connect bitlines and wordlines, then electrical connectivity is improved, but manufacturing precision requirements increase due to alignment at different height levels
Solution Approach 1:
The lower insulating structure is formed in advance to cover and define the positions of circuit devices and interconnection patterns before forming the upper structure. This preliminary action establishes reference planes and isolation boundaries that facilitate subsequent alignment of contact plugs and vertical memory structures at different height levels.
Solution Approach 2:
The lower insulating structure acts as an intermediary layer between the lower circuit interconnection structure and the upper vertical memory structure. It provides mechanical support, electrical isolation, and a reference plane that mediates the alignment between contact plugs and underlying connection patterns, reducing direct alignment requirements.
3Reliability
If multi-layer insulating structures are used to prevent defects, then reliability is improved, but device complexity increases
Solution Approach 1:
Different regions of the insulating structure have different properties tailored to local requirements. The lower insulating structure uses first and second materials with different dielectric properties to provide appropriate isolation and support in different zones. This local optimization prevents defects without requiring uniform complexity throughout the entire device.
Solution Approach 2:
The insulating structure comprises composite materials including first insulating material and second insulating material with different properties. This composite construction provides enhanced defect prevention through complementary properties of different materials while maintaining structural integrity and electrical isolation across the device.
Data Source
AI summary
A semiconductor device includes a contact plug forming a signal path electrically connecting a bitline or wordlines and an upper connection pattern to each other, a lower insulating structure includes first and second insulating portions; the contact plug penetrates through the second insulating portion and contacts the upper connection pattern; the first insulating portion includes first and second lower layers, the second lower layer having a thickness smaller than the first lower layer; the second insulating portion includes a first upper layer contacting the second lower layer and covering a portion of an upper surface of the upper connection pattern, and a second upper layer on the first upper layer, the second upper layer having a thickness greater than the first upper layer; and materials of the second lower layer and first upper layer is different from materials of the first lower layer and the second upper layer.