Vertical Memory Contacts for Dense 3D Interconnect Routing
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Solution Overview
Problem
Conventional 3D memory devices face challenges in efficiently coupling conductive lines to sense amplifiers due to traditional geometry, resulting in increased interconnection area and parasitic current loss, which limits interconnection density and increases the number of components.
Innovation Solution
The implementation of vertical contacts that allow direct multi-directional conductive lines to connect with circuitry components, eliminating the need for horizontal interconnections and reducing parasitic current loss by providing a more direct electrical path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional horizontal interconnection geometry is used to couple conductive lines to sense amplifiers, then the interconnection structure is simple to implement, but the interconnection area increases and parasitic current loss increases
Solution Approach 1:
The patent transitions from traditional horizontal interconnection geometry to a vertical interconnection structure. The vertical contact structure extends in the vertical dimension, allowing conductive lines to couple directly to sense amplifiers below without requiring extensive horizontal routing. This dimensional change reduces the lateral interconnection area while maintaining electrical connectivity.
Solution Approach 2:
The vertical contact structure merges the interconnection function with the memory cell stack structure. The contact extends vertically through the memory cell stack, combining the functions of electrical connection and structural integration, thereby reducing the need for separate horizontal interconnection layers and reducing overall interconnection area.
2Ease of manufacture
If traditional horizontal interconnection geometry is used to couple conductive lines to sense amplifiers, then the interconnection structure is simple to implement, but parasitic current loss increases
Solution Approach 1:
By changing from horizontal to vertical interconnection geometry, the patent creates a more direct electrical path between conductive lines and sense amplifiers. The vertical contact structure reduces the current path length and minimizes the number of interconnection interfaces, thereby reducing parasitic resistance and associated current loss.
Solution Approach 2:
The vertical contact structure extracts and eliminates the need for multiple horizontal interconnection layers and associated contact interfaces. By directly coupling conductive lines to sense amplifiers through the vertical path, the patent removes intermediate connection points that would otherwise contribute to parasitic current loss.
3Productivity
If vertical contacts are implemented to provide direct multi-directional connections, then interconnection density increases and parasitic current loss decreases, but the device complexity increases
Solution Approach 1:
The vertical contact structure serves multiple functions simultaneously: it provides electrical connection between conductive lines and sense amplifiers, acts as a structural element within the memory cell stack, and enables multi-directional coupling. This multi-functionality increases interconnection density while the modular design helps manage the associated complexity.
4Quantity of substance
If vertical contacts are implemented to provide direct connections, then the number of components is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The vertical contact structure merges multiple interconnection functions into a single integrated structure. By combining the electrical connection path and structural support function into one vertical element, the patent reduces the total number of separate components while the alignment is managed through integrated fabrication processes.
Data Source
AI summary
Embodiments herein relate to vertical contacts for semiconductor devices. For instance, a memory device having vertical contacts can comprise a substrate including circuitry components, a vertical stack of layers formed from repeating iterations of a group of layers disposed on the substrate, the group of layers comprising a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer including horizontal conductive lines formed along a horizontal plane in the second dielectric material layer, and vertical contacts coupled to the horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductive lines to the circuitry components.