Vertical 2-Transistor Memory Cell for Read Disturb Prevention
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Solution Overview
Problem
Conventional volatile memory devices face challenges in reducing memory cell size due to physical limitations and fabrication constraints, and require higher threshold voltages for write access transistors to prevent read disturb, which complicates their design and operation.
Innovation Solution
The use of separate access lines for each memory cell allows independent control of transistors during read and write operations, reducing the need for high threshold voltages and enabling smaller memory cell sizes while preventing adjacent transistor disturbance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory cell size is shrunk to increase storage density, then device storage density is improved, but physical limitations and fabrication constraints make it difficult to achieve further shrinkage
Solution Approach 1:
The patent transitions from planar 2D memory cell layout to a vertical 3D architecture where transistors are stacked above the substrate. The charge storage structure extends vertically with depth greater than its width, utilizing the third dimension (Z-axis) to increase storage capacity without expanding the footprint area, thereby achieving higher storage density while avoiding further 2D shrinkage limitations.
Solution Approach 2:
The patent implements a nested structure where the charge storage structure is positioned within and surrounded by multiple transistor components. The bit line transistor and word line transistor are arranged around the charge storage structure, with their channels wrapping around it. This nested arrangement maximizes space utilization and enables compact vertical integration.
2Device complexity
If the same access line is used to control multiple access transistors, then device complexity is reduced, but threshold voltage requirements become more stringent to prevent read disturb
Solution Approach 1:
The patent divides the access control function into separate bit line access lines and word line access lines, with each line dedicated to controlling specific transistors. The bit line access line controls the bit line transistor, while the word line access line controls the word line transistor. This segmentation allows independent threshold voltage optimization for each transistor type, enabling reliable read disturb prevention without requiring overly complex access line configurations.
Solution Approach 2:
The patent applies different threshold voltage characteristics to different transistors based on their specific functions. The bit line transistor is designed with threshold voltage characteristics optimized for write operations, while the word line transistor has characteristics optimized for read operations. This local quality differentiation allows each transistor to be tuned for its specific role, preventing read disturb without imposing uniform stringent requirements on all access transistors.
3Reliability
If separate access lines are used for each memory cell, then independent control of transistors is achieved and read disturb is prevented, but device complexity increases
Solution Approach 1:
The patent designs the bit line access lines and word line access lines to serve multiple functions. The same bit line access line controls bit line transistors across multiple memory cells, and the same word line access line controls word line transistors across multiple memory cells. This multi-functionality reduces the total number of access lines needed while still providing independent control for preventing read disturb in each individual memory cell.
Data Source
AI summary
Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.