Vertical Memory Device Double-Layered Channel Structure
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Solution Overview
Problem
As the degree of integration in vertical memory devices increases, improving operational reliability becomes a challenge due to higher resistance and leakage currents, particularly in the channel layer and ground selection transistor (GST) of these devices.
Innovation Solution
A vertical memory device is designed with a double-layered channel structure, where the first channel layer has a higher impurity concentration and serves as a p-well, and the second channel layer has a lower impurity concentration, forming a parallel connection with the vertical channel. This configuration includes a low resistance layer and an ohmic contact layer to reduce resistance and leakage current, while maintaining the driving properties of the GST.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration is increased to achieve higher vertical memory device performance, then the stacking number of memory cells and channel height are increased, but resistance and leakage current increase causing degraded operational reliability
Solution Approach 1:
The channel layer is divided into multiple segments with different impurity concentrations (first channel layer with higher impurity concentration and second channel layer with lower impurity concentration). This segmentation allows each segment to perform different functions: the first channel layer reduces resistance and leakage current, while the second channel layer maintains driving properties of the ground selection transistor, thereby resolving the contradiction between integration and reliability.
Solution Approach 2:
Different regions of the channel layer are assigned different impurity concentrations to optimize local properties. The first channel layer has higher impurity concentration specifically where resistance and leakage current need to be reduced, while the second channel layer has lower impurity concentration where driving properties need to be maintained. This local quality differentiation resolves the contradiction by addressing specific problems in specific regions rather than uniformly increasing integration throughout.
2Reliability
If a single channel layer structure is used, then device structure is simple, but resistance and leakage current cannot be effectively reduced
Solution Approach 1:
The channel layer is segmented into two distinct layers with different impurity concentrations. The first channel layer is configured to reduce resistance and leakage current, while the second channel layer is configured to maintain driving properties. This segmentation enables effective reduction of resistance and leakage current without requiring complex multi-layer structures, as only two layers are needed to achieve the desired effect.
Solution Approach 2:
The impurity concentration parameter is changed between the two channel layers. The first channel layer has a higher impurity concentration to reduce resistance and leakage current, while the second channel layer has a lower impurity concentration to maintain driving properties. This parameter change approach allows effective resistance and leakage current reduction while maintaining a relatively simple two-layer structure rather than requiring complex multi-layer configurations.
3Reliability
If impurity concentration is increased to reduce resistance, then resistance decreases, but driving properties of ground selection transistor deteriorate
Solution Approach 1:
The channel layer is segmented into two functional regions: the first channel layer with higher impurity concentration that reduces resistance and leakage current, and the second channel layer with lower impurity concentration that maintains the driving properties of the ground selection transistor. This segmentation allows resistance reduction in one region without deteriorating GST driving properties in another region, as the two functions are spatially separated within the double-layer structure.
Solution Approach 2:
Different impurity concentrations are applied locally to different regions of the channel layer. The first channel layer has higher impurity concentration locally where resistance and leakage current need to be reduced, while the second channel layer has lower impurity concentration locally where ground selection transistor driving properties need to be maintained. This local quality differentiation resolves the contradiction by allowing high impurity concentration only where it benefits resistance reduction, and low impurity concentration where it benefits GST operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the resistance and leakage current of the channel layer, enhancing the operational reliability and driving properties of the vertical memory device by optimizing the channel structure and layer configurations.
Implementation Method 1
an ohmic contact layer between the low resistance layer and the channel layer
Implementation Method 2
The ohmic contact layer and the channel layer may include polysilicon doped with p-type impurities. The impurity concentration of the ohmic contact layer may be greater than an impurity concentration of the channel layer.
Data Source
AI summary
According to example embodiments, a vertical memory device includes a low resistance layer on a lower insulation layer, a channel layer on the low resistance layer, a plurality of vertical channels on the channel layer, and a plurality of gate lines. The vertical channels extend in a first direction that is perpendicular with respect to a top surface of the channel layer. The gate lines surround outer sidewalls of the vertical channels, and are stacked in the first direction and are spaced apart from each other.