Vertical Memory Edge Region Step Structure Formation
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Solution Overview
Problem
In the manufacturing of vertical memory devices, the edge exposure wafer (EEW) process faces challenges in accurately forming step structures on the edge regions of substrates, leading to substrate contamination and inefficiencies due to the limitations of using a single target position for exposure, which results in steep slopes and increased tolerance errors.
Innovation Solution
A method involving multiple masks and etching processes is employed to form step structures on both the main and edge regions of substrates, using multiple target positions for exposure to create a gentler slope and reduce tolerance errors, thereby increasing the area for forming steps and improving the precision of the mold structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single target position is used for EEW process, then the process is simple, but the slope becomes steep and tolerance errors increase
Solution Approach 1:
The patent divides the EEW process into multiple exposure steps with different target positions (first target position and second target position). This segmentation allows the formation of step structures with gentler slopes by progressively exposing different regions of the edge region, thereby reducing tolerance errors and improving manufacturing precision without excessive complexity increase
Solution Approach 2:
The patent introduces a new dimension to the EEW process by using multiple target positions along the edge region rather than a single position. This dimensional expansion enables better control over step structure formation, creating gentler slopes and reducing tolerance accumulation while maintaining reasonable process complexity
2Object-affected harmful factors
If EEW process is performed to remove layers and structures from edge region, then substrate contamination is prevented, but manufacturing precision of step structures decreases
Solution Approach 1:
The patent segments the edge region exposure into multiple controlled steps with different target positions, allowing precise formation of step structures while still achieving complete removal of layers and structures from the edge region. This prevents substrate contamination while maintaining high manufacturing precision through controlled, progressive exposure
Solution Approach 2:
The patent applies different exposure conditions to different local regions of the edge region by using multiple target positions. This local quality approach ensures that each region receives appropriate exposure to form precise step structures while still achieving the overall goal of preventing substrate contamination through complete edge region processing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of vertical memory device manufacturing by reducing substrate contamination and improving the accuracy of step structures, leading to more reliable and efficient device production.
Implementation Method 1
A first mask may be formed on the preliminary first mold structure. The first mask may expose an upper surface of the preliminary first mold structure on a region from a boundary of the substrate to a first target position.
Implementation Method 2
The insulation layers and the sacrificial layers may be partially etched using the first mask as an etching mask to form a preliminary second mold structure including a preliminary step structure.
Data Source
AI summary
A method of manufacturing a vertical memory device includes forming a preliminary first mold structure on a substrate, which includes main and edge regions, and the first preliminary mold structure including alternating insulation and sacrificial layers, forming a first mask on the preliminary first mold structure to expose the preliminary first mold structure between a boundary of the substrate and a first target position, partially etching the insulation and sacrificial layers using the first mask to form a preliminary second mold structure, forming a second mask on the preliminary second mold structure to expose the preliminary second mold structure between the boundary of the substrate and a second target position different from the first target position, and partially etching the insulation layers and the sacrificial layers using the second mask.