Vertical Memory Epitaxial Layer Formation
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Solution Overview
Problem
There is a need for a method to form an epitaxial layer serving as a source/drain layer in the peripheral circuit region of VNAND flash memory devices, which is not efficiently addressed by existing technologies.
Innovation Solution
A vertical memory device is developed with a gate structure and epitaxial layers formed using a selective epitaxial growth (SEG) process, where the first epitaxial layer serves as a channel in the cell region and the second epitaxial layer serves as a source/drain layer in the peripheral circuit region, both formed simultaneously using the same SEG process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a selective epitaxial growth (SEG) process is used to form an epitaxial layer in the peripheral circuit region, then the structural integrity and material consistency are improved, but the manufacturing process complexity increases
Solution Approach 1:
The substrate is divided into a cell region and a peripheral circuit region, with each region receiving targeted epitaxial growth treatment. The SEG process selectively forms epitaxial layers only in the peripheral circuit region where needed, while the cell region maintains its original structure. This segmentation allows the patent to achieve region-specific structural integrity without applying complex processing to the entire device.
Solution Approach 2:
The patent applies epitaxial growth selectively to the peripheral circuit region rather than uniformly across the entire substrate. This local quality approach ensures that epitaxial layers with consistent material properties are formed only where required for source/drain structures, while leaving the cell region unchanged. The local application of SEG process resolves the contradiction by providing material consistency only where structurally necessary.
2Manufacturing precision
If separate processes are used to form epitaxial layers in different regions, then the manufacturing precision is improved, but the productivity decreases
Solution Approach 1:
The patent combines the formation of epitaxial layers in the peripheral circuit region with the existing SEG process used for channel formation in the cell region. By merging these operations into a single selective epitaxial growth step, the patent achieves precise control over epitaxial layer formation in different regions without requiring separate processing steps. This merging maintains manufacturing precision while improving productivity by reducing the total number of process steps.
Solution Approach 2:
The SEG process is designed to serve multiple functions simultaneously: it forms channels in the cell region and forms source/drain epitaxial layers in the peripheral circuit region in a single operation. This multi-functionality allows the patent to achieve precise epitaxial layer formation across different device regions without sacrificing manufacturing efficiency, as the same process accomplishes multiple structural objectives.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process and ensures that the epitaxial layers consist of the same material, enhancing the structural integrity and performance of the vertical memory device.
Implementation Method 1
A semiconductor pattern serving as a channel of a transistor including a GSL in a cell region of a VNAND flash memory device may be formed by a selective epitaxial growth (SEG) process. It is required to develop a method of forming an epitaxial layer serving as a source/drain layer in a peripheral circuit region of the VNAND flash memory device.
Data Source
AI summary
A vertical memory device includes a gate structure on a peripheral circuit region of a substrate, the substrate including a cell region and the peripheral circuit region, and the gate structure including a first gate electrode, second, third, and fourth gate electrodes sequentially disposed at a plurality of levels, respectively, on the cell region of the substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a first epitaxial layer extending through the second gate electrode on the cell region of the substrate, a channel extending through the third and fourth gate electrodes in the vertical direction on the first epitaxial layer, and a second epitaxial layer on a portion of the peripheral circuit region of the substrate adjacent the gate structure.