Vertical Memory Device Etching Defect Resolution
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Solution Overview
Problem
The existing methods for manufacturing vertical memory devices face defects related to the etching process of channel holes, which affect the integration and performance of semiconductor memory devices.
Innovation Solution
The proposed solution involves a vertical memory device design with a specific structure that includes stacked gate electrode layers, isolation insulating layers, and vertically penetrating holes with channel and support structures, where the channel holes and support holes have the same diameter and are arranged with uniform distances, using materials that differ between the channel and support structures, to address the etching process defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional planar transistor structure is used, then manufacturing process is simpler, but degree of integration is limited
Solution Approach 1:
The patent transitions from conventional planar (2D) transistor structures to vertical (3D) transistor structures by stacking multiple gate electrode layers and channel structures in the vertical direction. This dimensional change enables higher degree of integration within the same footprint area, allowing more memory cells to be packed into the semiconductor device while maintaining manufacturability through adapted fabrication processes.
2Ease of manufacture
If channel holes are etched using conventional methods, then manufacturing process is established, but etching defects occur affecting device reliability
Solution Approach 1:
The patent modifies etching process parameters including using selective etching conditions that exploit differences in etch rates between various material layers. By controlling etch selectivity, temperature, pressure, and chemical composition, the patent achieves defect-free channel hole formation while maintaining compatibility with existing manufacturing infrastructure. The uniform diameter of vertical holes throughout the cell region indicates successful parameter optimization.
Solution Approach 2:
The patent introduces intermediate layers such as mandrel structures and sacrificial layers that facilitate the etching process. These intermediary elements enable precise formation of vertical channel holes with uniform dimensions by providing temporary structural support and etch stopping layers, thereby improving device reliability without complicating the overall manufacturing flow.
3Quantity of substance
If vertical memory device structure is implemented, then degree of integration increases, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the vertical memory structure into discrete, repeatable units including stacked gate electrode layers, isolated channel structures, and regularly spaced vertical holes. This segmentation approach allows each component to be manufactured with controlled precision using standardized processes, reducing overall manufacturing complexity while achieving high degree of integration. The uniform spacing and dimensions of vertical structures indicate successful implementation of this segmentation strategy.
Data Source
AI summary
A vertical memory device and a method of manufacturing such device are provided. The vertical memory device may include a plurality of gate electrode layers stacked in a cell region of a semiconductor substrate; a plurality of upper isolation insulating layers dividing an uppermost gate electrode layer among the plurality of gate electrode layers, extending in a first direction; a plurality of vertical holes arranged to have any two adjacent vertical holes to have a uniform distance from each other throughout the cell region and including a plurality of channel holes penetrating through the plurality of gate electrode layers disposed between the plurality of upper isolation insulating layers and a plurality of first support holes penetrating through the plurality of upper insulating layers; a plurality of channel structures disposed in the plurality of channel holes; and a plurality of first support structures disposed in the plurality of first support holes.